Add divider stub and fu op encodings

include/ariane_pkg.sv

@@ -93,7 +93,11 @@ package ariane_pkg;
                                // CSR functions
                                MRET, SRET, ECALL, WFI, FENCE_I, SFENCE_VMA, CSR_WRITE, CSR_READ, CSR_SET, CSR_CLEAR,
                                // LSU functions
-                               LD, SD, LW, LWU, SW, LH, LHU, SH, LB, SB, LBU
+                               LD, SD, LW, LWU, SW, LH, LHU, SH, LB, SB, LBU,
+                               // Multiplications
+                               MUL, MULH, MULHU, MULHSU, MULW,
+                               // Divisions
+                               DIV, DIVU, REM, REMU, DIV, DIVU, DIVW, DIVWU, REM, REMU, REMW, REMWU
                              } fu_op;
 
     typedef struct packed {

src/alu.sv

@@ -36,8 +36,8 @@ module alu
     output logic                     alu_ready_o,
     output logic [TRANS_ID_BITS-1:0] alu_trans_id_o
 );
-    // ALU is a single cycle instructions, hence it is always ready
 
+    // ALU is a single cycle instructions, hence it is always ready
     assign alu_ready_o    = 1'b1;
     assign alu_valid_o    = alu_valid_i;
     assign alu_trans_id_o = trans_id_i;

src/div.sv

@@ -0,0 +1,27 @@
+// Author:
+//
+// Date: 25.07.2017
+// Description: Ariane Divider
+//
+//
+// Copyright (C) 2017 ETH Zurich, University of Bologna
+// All rights reserved.
+//
+// This code is under development and not yet released to the public.
+// Until it is released, the code is under the copyright of ETH Zurich and
+// the University of Bologna, and may contain confidential and/or unpublished
+// work. Any reuse/redistribution is strictly forbidden without written
+// permission from ETH Zurich.
+//
+// Bug fixes and contributions will eventually be released under the
+// SolderPad open hardware license in the context of the PULP platform
+// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the
+// University of Bologna.
+//
+module div (
+    input logic clk_i,    // Clock
+    input logic rst_ni,   // Asynchronous reset active low
+
+);
+
+endmodule

src/mult.sv

@@ -1,7 +1,7 @@
 // Author: Pasquale Davide Schiavone <pschiavo@iis.ee.ethz.ch>
 //
 // Date: 05.06.2017
-// Description: Ariane MULT
+// Description: Ariane Multiplier
 //
 //
 // Copyright (C) 2017 ETH Zurich, University of Bologna
@@ -27,18 +27,16 @@ module mult
     input  logic                     rst_ni,
     input  logic [TRANS_ID_BITS-1:0] trans_id_i,
     input  logic                     mult_valid_i,
-    input  logic                     is_low_part_i,
+    input  fu_op                     operator_i,
     input  logic [63:0]              operand_a_i,
     input  logic [63:0]              operand_b_i,
-    input  logic                     sign_a_i,
-    input  logic                     sign_b_i,
+    output logic [63:0]              result_o,
     output logic [63:0]              result_o,
     output logic                     mult_valid_o,
     output logic                     mult_ready_o,
     output logic [TRANS_ID_BITS-1:0] mult_trans_id_o
 );
     // MUL and MULH is a two cycle instructions
-
     logic signed [63:0]  result_mult;
     logic signed [63:0]  result_multh;
     enum logic {FIRST_CYCLE, SECOND_CYCLE} multCS, multNS;
@@ -75,7 +73,7 @@ module mult
                 mult_ready_o = 1'b1;
             end
             default:;
-        endcase // multCS
+        endcase
     end
 
     always_ff @(posedge clk_i or negedge rst_ni) begin
@@ -106,7 +104,7 @@ module mult_datapath
     assign operand_a_ext  = $signed({sign_a_i & operand_a_i[63], operand_a_i});
     assign operand_b_ext  = $signed({sign_b_i & operand_b_i[63], operand_b_i});
 
-    assign mult_result    = operand_a_ext*operand_b_ext;
+    assign mult_result    = operand_a_ext * operand_b_ext;
 
     assign result_low_o   = $signed(mult_result[ 63: 0]);
     assign result_high_o  = $signed(mult_result[127:64]);