Add support for device tree

- compiling
- loading

.editorconfig

@@ -6,8 +6,6 @@ root = true
 end_of_line = lf
 insert_final_newline = true
 trim_trailing_whitespace = true
-indent_style = space
-indent_size = 4
 max_line_length = off
 # 4 space indentation
 [*.{sv, svh, v, vhd}]

.gitignore

@@ -10,4 +10,5 @@ transcript
 wlft*
 *nfs*
 src/moore.sv
-*.sig
+*.sig
+*.dtb

Makefile

@@ -71,6 +71,9 @@ uvm-flags = +UVM_NO_RELNOTES
 # Iterate over all include directories and write them with +incdir+ prefixed
 # +incdir+ works for Verilator and QuestaSim
 list_incdir = $(foreach dir, ${incdir}, +incdir+$(dir))
+# Device Tree Compiler
+DTC = dtc
+
 # create library if it doesn't exist
 
 # # Build the TB and module using QuestaSim
@@ -114,11 +117,11 @@ $(library):
 	# Create the library
 	vlib${questa_version} ${library}
 
-sim: build
+sim: build ariane_tb.dtb
 	vsim${questa_version} -lib ${library} ${top_level}_optimized +UVM_TESTNAME=${test_case} +BASEDIR=$(riscv-test-dir) \
 	+ASMTEST=$(riscv-test)  $(uvm-flags) +UVM_VERBOSITY=HIGH -coverage -classdebug -do "do tb/wave/wave_core.do"
 
-simc: build
+simc: build ariane_tb.dtb
 	vsim${questa_version} -c -lib ${library} ${top_level}_optimized +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
 	 +BASEDIR=$(riscv-test-dir) +UVM_VERBOSITY=LOW  $(uvm-flags) +ASMTEST=$(riscv-test) -coverage -classdebug
 
@@ -160,6 +163,10 @@ build-moore:
 build-tests:
 	cd riscv-tests && autoconf && ./configure --prefix=/home/zarubaf/riscv && make isa -j8
 
+# Compile device tree
+ariane_tb.dtb:  ariane_tb.dts
+	$(DTC) -I dts -O dtb ariane_tb.dts > ariane_tb.dtb
+
 # User Verilator to lint the target
 lint:
 	verilator $(ariane_pkg) $(src) --lint-only \

ariane_tb.dts

@@ -0,0 +1,46 @@
+/dts-v1/;
+
+/ {
+  #address-cells = <2>;
+  #size-cells = <2>;
+  compatible = "ucbbar,spike-bare-dev";
+  model = "ucbbar,spike-bare";
+  cpus {
+    #address-cells = <1>;
+    #size-cells = <0>;
+    timebase-frequency = <10000000>;
+    CPU0: cpu@0 {
+      device_type = "cpu";
+      reg = <0>;
+      status = "okay";
+      compatible = "riscv";
+      riscv,isa = "rv64ic";
+      mmu-type = "riscv,sv39";
+      clock-frequency = <1000000000>;
+      CPU0_intc: interrupt-controller {
+        #interrupt-cells = <1>;
+        interrupt-controller;
+        compatible = "riscv,cpu-intc";
+      };
+    };
+  };
+  memory@80000000 {
+    device_type = "memory";
+    reg = <0x0 0x80000000 0x0 0x80000000>;
+  };
+  soc {
+    #address-cells = <2>;
+    #size-cells = <2>;
+    compatible = "ucbbar,spike-bare-soc", "simple-bus";
+    ranges;
+    clint@2000000 {
+      compatible = "riscv,clint0";
+      interrupts-extended = <&CPU0_intc 3 &CPU0_intc 7 >;
+      reg = <0x0 0x2000000 0x0 0xc0000>;
+    };
+    uart@3000000 {
+        compatible = "sifive,uart0";
+        reg = <0x0 0x3000000 0x0 0x3000000>;
+    };
+  };
+};

tb

@@ -1 +1 @@
-Subproject commit 57f582dc1e22511654e1d2af19bd4082403ee6d8
+Subproject commit 03d8a82317fb568d0ab2d679a077befaff51f98c