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Update Makefile with path to ethernet submodule Verilog files

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This commit is contained in:
Jonathan Richard Robert Kimmitt 2019-01-29 08:51:23 +00:00
parent b5ab439a96
commit 4a62b8c2ba
2 changed files with 2 additions and 2 deletions
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2
Makefile
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@ -142,7 +142,7 @@ src := $(addprefix $(root-dir), $(src))
uart_src := $(wildcard fpga/src/apb_uart/src/*.vhd)
uart_src := $(addprefix $(root-dir), $(uart_src))
fpga_src := $(wildcard fpga/src/*.sv) $(wildcard fpga/src/bootrom/*.sv)
fpga_src := $(wildcard fpga/src/*.sv) $(wildcard fpga/src/bootrom/*.sv) $(wildcard fpga/src/ariane-ethernet/*.sv)
fpga_src := $(addprefix $(root-dir), $(fpga_src))
# look for testbenches

2
fpga/src/ariane-ethernet

@ -1 +1 @@
Subproject commit c8fd89437d250b59ead30c233cf2a279be1c48c7
Subproject commit 4ea1127e5d2d0b5d3bd281542066b4a4e4d2fe50