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Use only one Flist for all configurations (#1012)

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This commit is contained in:
JeanRochCoulon 2022-12-13 09:31:26 +01:00 • committed by GitHub
parent 28c620a93a
commit 4b33e69a10
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GPG key ID: 4AEE18F83AFDEB23
11 changed files with 18 additions and 820 deletions
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13
Makefile
View file

@ -87,6 +87,9 @@ endif
# target takes one of the following cva6 hardware configuration:
# cv64a6_imafdc_sv39, cv32a6_imac_sv0, cv32a6_imac_sv32, cv32a6_imafc_sv32, cv32a6_ima_sv32_fpga
target ?= cv64a6_imafdc_sv39
ifndef TARGET_CFG
export TARGET_CFG = $(target)
endif
# Sources
# Package files -> compile first
@ -279,7 +282,7 @@ endif
vcs_build: $(dpi-library)/ariane_dpi.so
mkdir -p $(vcs-library)
cd $(vcs-library) &&\
vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog +define+$(defines) -f ../core/Flist.$(target) &&\
vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog +define+$(defines) -f ../core/Flist.cva6 &&\
vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog +define+$(defines) $(filter %.sv,$(ariane_pkg)) +incdir+core/include/+$(VCS_HOME)/etc/uvm-1.2/dpi &&\
vhdlan $(if $(VERDI), -kdb,) -full64 -nc $(filter %.vhd,$(uart_src)) &&\
vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -assert svaext +define+$(defines) $(filter %.sv,$(src)) +incdir+../vendor/pulp-platform/common_cells/include/+../corev_apu/axi/include/+../corev_apu/register_interface/include/ &&\
@ -301,7 +304,7 @@ $(library)/.build-srcs: $(library)
# Suppress message that always_latch may not be checked thoroughly by QuestaSim.
$(VCOM) $(compile_flag_vhd) -work $(library) -pedanticerrors $(filter %.vhd,$(uart_src))
$(VLOG) $(compile_flag) -timescale "1ns / 1ns" -work $(library) -pedanticerrors $(filter %.sv,$(src)) $(list_incdir) -suppress 2583
$(VLOG) $(compile_flag) -timescale "1ns / 1ns" -work $(library) -pedanticerrors -f ../core/Flist.$(target) $(list_incdir) -suppress 2583
$(VLOG) $(compile_flag) -timescale "1ns / 1ns" -work $(library) -pedanticerrors -f ../core/Flist.cva6 $(list_incdir) -suppress 2583
touch $(library)/.build-srcs
# build TBs
@ -432,7 +435,7 @@ XRUN_COMP = $(XRUN_COMP_FLAGS) \
$(filter %.sv, $(ariane_pkg)) \
$(filter %.vhd, $(uart_src)) \
$(filter %.sv, $(src)) \
-f ../core/Flist.$(target) \
-f ../core/Flist.cva6 \
$(filter %.sv, $(XRUN_TB)) \
XRUN_RUN = $(XRUN_RUN_FLAGS) \
@ -536,7 +539,7 @@ xrun-ci: xrun-asm-tests xrun-amo-tests xrun-mul-tests xrun-fp-tests xrun-benchma
# verilator-specific
verilate_command := $(verilator) \
-f core/Flist.$(target) \
-f core/Flist.cva6 \
$(filter-out %.vhd, $(ariane_pkg)) \
$(filter-out core/fpu_wrap.sv, $(filter-out %.vhd, $(src))) \
+define+$(defines)$(if $(TRACE_FAST),+VM_TRACE)$(if $(TRACE_COMPACT),+VM_TRACE+VM_TRACE_FST) \
@ -715,7 +718,7 @@ check-torture:
grep 'All signatures match for $(test-location)' $(riscv-torture-dir)/$(test-location).log
diff -s $(riscv-torture-dir)/$(test-location).spike.sig $(riscv-torture-dir)/$(test-location).rtlsim.sig
src_flist := $(addprefix $(root-dir), $(shell cat core/Flist.$(target)|grep "$\{CVA6_REPO_DIR.\+sv"|sed "s/.*CVA6_REPO_DIR..//"))
src_flist := $(addprefix $(root-dir), $(shell cat core/Flist.cva6|grep "$\{CVA6_REPO_DIR.\+sv"|sed "s/.*CVA6_REPO_DIR..//"|sed "s/..TARGET_CFG./$(target)/"))
fpga_filter := $(addprefix $(root-dir), corev_apu/bootrom/bootrom.sv)
fpga_filter += $(addprefix $(root-dir), core/include/instr_tracer_pkg.sv)
fpga_filter += $(addprefix $(root-dir), src/util/ex_trace_item.sv)

161
core/Flist.cv32a60x
View file

@ -1,161 +0,0 @@
//////////////////////////////////////////////////////////////////////////////
//
// Copyright 2022 OpenHW Group
//
// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// https://solderpad.org/licenses/
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
//
///////////////////////////////////////////////////////////////////////////////
//
// Manifest for the CVA6 CORE RTL model.
// - This is a CORE-ONLY manifest.
// - Relevent synthesis and simulation scripts/Makefiles must set the shell
// ENV variable CVA6_REPO_DIR.
//
///////////////////////////////////////////////////////////////////////////////
+define+WT_DCACHE
+incdir+${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/include/
+incdir+${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/
+incdir+${CVA6_REPO_DIR}/common/local/util/
${CVA6_REPO_DIR}/core/include/cv32a60x_config_pkg.sv
${CVA6_REPO_DIR}/core/include/riscv_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_dm_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_pkg.sv
// TODO: ariane_axi_pkg is dependent on this.
${CVA6_REPO_DIR}/corev_apu/axi/src/axi_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_rvfi_pkg.sv
// Packages
${CVA6_REPO_DIR}/core/include/ariane_axi_pkg.sv
${CVA6_REPO_DIR}/core/include/wt_cache_pkg.sv
${CVA6_REPO_DIR}/core/include/std_cache_pkg.sv
${CVA6_REPO_DIR}/core/include/axi_intf.sv
${CVA6_REPO_DIR}/core/include/instr_tracer_pkg.sv
//CVXIF
${CVA6_REPO_DIR}/core/include/cvxif_pkg.sv
${CVA6_REPO_DIR}/core/cvxif_example/include/cvxif_instr_pkg.sv
${CVA6_REPO_DIR}/core/cvxif_fu.sv
${CVA6_REPO_DIR}/core/cvxif_example/cvxif_example_coprocessor.sv
${CVA6_REPO_DIR}/core/cvxif_example/instr_decoder.sv
// Common Cells
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/cf_math_pkg.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/fifo_v3.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/lfsr.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/lzc.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/shift_reg.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/unread.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/popcount.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/exp_backoff.sv
// Common Cells for example coprocessor
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/counter.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/delta_counter.sv
// Floating point unit
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_pkg.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_cast_multi.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_classifier.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_divsqrt_multi.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_fma_multi.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_fma.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_noncomp.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_opgroup_block.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_opgroup_fmt_slice.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_opgroup_multifmt_slice.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_rounding.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_top.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv
// Top-level source files (not necessarily instantiated at the top of the cva6).
${CVA6_REPO_DIR}/core/ariane.sv
${CVA6_REPO_DIR}/core/cva6.sv
${CVA6_REPO_DIR}/core/alu.sv
// Note: depends on fpnew_pkg, above
${CVA6_REPO_DIR}/core/fpu_wrap.sv
${CVA6_REPO_DIR}/core/branch_unit.sv
${CVA6_REPO_DIR}/core/compressed_decoder.sv
${CVA6_REPO_DIR}/core/controller.sv
${CVA6_REPO_DIR}/core/csr_buffer.sv
${CVA6_REPO_DIR}/core/csr_regfile.sv
${CVA6_REPO_DIR}/core/decoder.sv
${CVA6_REPO_DIR}/core/ex_stage.sv
${CVA6_REPO_DIR}/core/instr_realign.sv
${CVA6_REPO_DIR}/core/id_stage.sv
${CVA6_REPO_DIR}/core/issue_read_operands.sv
${CVA6_REPO_DIR}/core/issue_stage.sv
${CVA6_REPO_DIR}/core/load_unit.sv
${CVA6_REPO_DIR}/core/load_store_unit.sv
${CVA6_REPO_DIR}/core/lsu_bypass.sv
${CVA6_REPO_DIR}/core/mult.sv
${CVA6_REPO_DIR}/core/multiplier.sv
${CVA6_REPO_DIR}/core/serdiv.sv
${CVA6_REPO_DIR}/core/perf_counters.sv
${CVA6_REPO_DIR}/core/ariane_regfile_ff.sv
${CVA6_REPO_DIR}/core/re_name.sv
// NOTE: scoreboard.sv modified for DSIM (unchanged for other simulators)
${CVA6_REPO_DIR}/core/scoreboard.sv
${CVA6_REPO_DIR}/core/store_buffer.sv
${CVA6_REPO_DIR}/core/amo_buffer.sv
${CVA6_REPO_DIR}/core/store_unit.sv
${CVA6_REPO_DIR}/core/commit_stage.sv
${CVA6_REPO_DIR}/core/axi_shim.sv
// What is "frontend"?
${CVA6_REPO_DIR}/core/frontend/btb.sv
${CVA6_REPO_DIR}/core/frontend/bht.sv
${CVA6_REPO_DIR}/core/frontend/ras.sv
${CVA6_REPO_DIR}/core/frontend/instr_scan.sv
${CVA6_REPO_DIR}/core/frontend/instr_queue.sv
${CVA6_REPO_DIR}/core/frontend/frontend.sv
// Cache subsystem
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_ctrl.sv
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_mem.sv
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_missunit.sv
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_wbuffer.sv
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache.sv
${CVA6_REPO_DIR}/core/cache_subsystem/cva6_icache.sv
${CVA6_REPO_DIR}/core/cache_subsystem/wt_cache_subsystem.sv
${CVA6_REPO_DIR}/core/cache_subsystem/wt_axi_adapter.sv
// Physical Memory Protection
// NOTE: pmp.sv modified for DSIM (unchanged for other simulators)
${CVA6_REPO_DIR}/core/pmp/src/pmp.sv
${CVA6_REPO_DIR}/core/pmp/src/pmp_entry.sv
// Tracer (behavioral code, not RTL)
${CVA6_REPO_DIR}/common/local/util/instr_tracer_if.sv
${CVA6_REPO_DIR}/common/local/util/instr_tracer.sv
${CVA6_REPO_DIR}/common/local/util/tc_sram_wrapper.sv
${CVA6_REPO_DIR}/corev_apu/src/tech_cells_generic/src/rtl/tc_sram.sv
${CVA6_REPO_DIR}/common/local/util/sram.sv
// MMU Sv32
${CVA6_REPO_DIR}/core/mmu_sv32/cva6_mmu_sv32.sv
${CVA6_REPO_DIR}/core/mmu_sv32/cva6_ptw_sv32.sv
${CVA6_REPO_DIR}/core/mmu_sv32/cva6_tlb_sv32.sv
// end of manifest

154
core/Flist.cv32a6_ima_sv32_fpga
View file

@ -1,154 +0,0 @@
//////////////////////////////////////////////////////////////////////////////
//
// Copyright 2021 OpenHW Group
//
// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// https://solderpad.org/licenses/
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
//
///////////////////////////////////////////////////////////////////////////////
//
// Manifest for the CVA6 CORE RTL model.
// - This is a CORE-ONLY manifest.
// - Relevent synthesis and simulation scripts/Makefiles must set the shell
// ENV variable CVA6_REPO_DIR.
//
///////////////////////////////////////////////////////////////////////////////
+define+WT_DCACHE
+incdir+${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/include/
+incdir+${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/
+incdir+${CVA6_REPO_DIR}/common/local/util/
${CVA6_REPO_DIR}/core/include/cv32a6_imac_sv0_config_pkg.sv
${CVA6_REPO_DIR}/core/include/riscv_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_dm_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_pkg.sv
// TODO: ariane_axi_pkg is dependent on this.
${CVA6_REPO_DIR}/corev_apu/axi/src/axi_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_rvfi_pkg.sv
// Packages
${CVA6_REPO_DIR}/core/include/ariane_axi_pkg.sv
${CVA6_REPO_DIR}/core/include/wt_cache_pkg.sv
${CVA6_REPO_DIR}/core/include/std_cache_pkg.sv
${CVA6_REPO_DIR}/core/include/axi_intf.sv
${CVA6_REPO_DIR}/core/include/instr_tracer_pkg.sv
//CVXIF
${CVA6_REPO_DIR}/core/include/cvxif_pkg.sv
${CVA6_REPO_DIR}/core/cvxif_fu.sv
// Common Cells
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/cf_math_pkg.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/fifo_v3.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/lfsr.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/lzc.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/shift_reg.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/unread.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/popcount.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/exp_backoff.sv
// Floating point unit
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_pkg.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_cast_multi.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_classifier.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_divsqrt_multi.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_fma_multi.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_fma.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_noncomp.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_opgroup_block.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_opgroup_fmt_slice.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_opgroup_multifmt_slice.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_rounding.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_top.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv
// Top-level source files (not necessarily instantiated at the top of the cva6).
${CVA6_REPO_DIR}/core/ariane.sv
${CVA6_REPO_DIR}/core/cva6.sv
${CVA6_REPO_DIR}/core/alu.sv
// Note: depends on fpnew_pkg, above
${CVA6_REPO_DIR}/core/fpu_wrap.sv
${CVA6_REPO_DIR}/core/branch_unit.sv
${CVA6_REPO_DIR}/core/compressed_decoder.sv
${CVA6_REPO_DIR}/core/controller.sv
${CVA6_REPO_DIR}/core/csr_buffer.sv
${CVA6_REPO_DIR}/core/csr_regfile.sv
${CVA6_REPO_DIR}/core/decoder.sv
${CVA6_REPO_DIR}/core/ex_stage.sv
${CVA6_REPO_DIR}/core/instr_realign.sv
${CVA6_REPO_DIR}/core/id_stage.sv
${CVA6_REPO_DIR}/core/issue_read_operands.sv
${CVA6_REPO_DIR}/core/issue_stage.sv
${CVA6_REPO_DIR}/core/load_unit.sv
${CVA6_REPO_DIR}/core/load_store_unit.sv
${CVA6_REPO_DIR}/core/lsu_bypass.sv
${CVA6_REPO_DIR}/core/mult.sv
${CVA6_REPO_DIR}/core/multiplier.sv
${CVA6_REPO_DIR}/core/serdiv.sv
${CVA6_REPO_DIR}/core/perf_counters.sv
${CVA6_REPO_DIR}/core/ariane_regfile_ff.sv
${CVA6_REPO_DIR}/core/re_name.sv
// NOTE: scoreboard.sv modified for DSIM (unchanged for other simulators)
${CVA6_REPO_DIR}/core/scoreboard.sv
${CVA6_REPO_DIR}/core/store_buffer.sv
${CVA6_REPO_DIR}/core/amo_buffer.sv
${CVA6_REPO_DIR}/core/store_unit.sv
${CVA6_REPO_DIR}/core/commit_stage.sv
${CVA6_REPO_DIR}/core/axi_shim.sv
// What is "frontend"?
${CVA6_REPO_DIR}/core/frontend/btb.sv
${CVA6_REPO_DIR}/core/frontend/bht.sv
${CVA6_REPO_DIR}/core/frontend/ras.sv
${CVA6_REPO_DIR}/core/frontend/instr_scan.sv
${CVA6_REPO_DIR}/core/frontend/instr_queue.sv
${CVA6_REPO_DIR}/core/frontend/frontend.sv
// Cache subsystem
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_ctrl.sv
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_mem.sv
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_missunit.sv
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_wbuffer.sv
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache.sv
${CVA6_REPO_DIR}/core/cache_subsystem/cva6_icache.sv
${CVA6_REPO_DIR}/core/cache_subsystem/wt_cache_subsystem.sv
${CVA6_REPO_DIR}/core/cache_subsystem/wt_axi_adapter.sv
// Physical Memory Protection
// NOTE: pmp.sv modified for DSIM (unchanged for other simulators)
${CVA6_REPO_DIR}/core/pmp/src/pmp.sv
${CVA6_REPO_DIR}/core/pmp/src/pmp_entry.sv
// Tracer (behavioral code, not RTL)
${CVA6_REPO_DIR}/common/local/util/instr_tracer_if.sv
${CVA6_REPO_DIR}/common/local/util/instr_tracer.sv
${CVA6_REPO_DIR}/common/local/util/tc_sram_wrapper.sv
${CVA6_REPO_DIR}/corev_apu/src/tech_cells_generic/src/rtl/tc_sram.sv
${CVA6_REPO_DIR}/common/local/util/sram.sv
// MMU Sv32
${CVA6_REPO_DIR}/core/mmu_sv32/cva6_mmu_sv32.sv
${CVA6_REPO_DIR}/core/mmu_sv32/cva6_ptw_sv32.sv
${CVA6_REPO_DIR}/core/mmu_sv32/cva6_tlb_sv32.sv
// end of manifest

154
core/Flist.cv32a6_imac_sv0
View file

@ -1,154 +0,0 @@
//////////////////////////////////////////////////////////////////////////////
//
// Copyright 2021 OpenHW Group
//
// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// https://solderpad.org/licenses/
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
//
///////////////////////////////////////////////////////////////////////////////
//
// Manifest for the CVA6 CORE RTL model.
// - This is a CORE-ONLY manifest.
// - Relevent synthesis and simulation scripts/Makefiles must set the shell
// ENV variable CVA6_REPO_DIR.
//
///////////////////////////////////////////////////////////////////////////////
+define+WT_DCACHE
+incdir+${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/include/
+incdir+${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/
+incdir+${CVA6_REPO_DIR}/common/local/util/
${CVA6_REPO_DIR}/core/include/cv32a6_imac_sv0_config_pkg.sv
${CVA6_REPO_DIR}/core/include/riscv_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_dm_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_pkg.sv
// TODO: ariane_axi_pkg is dependent on this.
${CVA6_REPO_DIR}/corev_apu/axi/src/axi_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_rvfi_pkg.sv
// Packages
${CVA6_REPO_DIR}/core/include/ariane_axi_pkg.sv
${CVA6_REPO_DIR}/core/include/wt_cache_pkg.sv
${CVA6_REPO_DIR}/core/include/std_cache_pkg.sv
${CVA6_REPO_DIR}/core/include/axi_intf.sv
${CVA6_REPO_DIR}/core/include/instr_tracer_pkg.sv
//CVXIF
${CVA6_REPO_DIR}/core/include/cvxif_pkg.sv
${CVA6_REPO_DIR}/core/cvxif_fu.sv
// Common Cells
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/cf_math_pkg.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/fifo_v3.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/lfsr.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/lzc.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/shift_reg.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/unread.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/popcount.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/exp_backoff.sv
// Floating point unit
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_pkg.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_cast_multi.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_classifier.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_divsqrt_multi.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_fma_multi.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_fma.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_noncomp.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_opgroup_block.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_opgroup_fmt_slice.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_opgroup_multifmt_slice.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_rounding.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_top.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv
// Top-level source files (not necessarily instantiated at the top of the cva6).
${CVA6_REPO_DIR}/core/ariane.sv
${CVA6_REPO_DIR}/core/cva6.sv
${CVA6_REPO_DIR}/core/alu.sv
// Note: depends on fpnew_pkg, above
${CVA6_REPO_DIR}/core/fpu_wrap.sv
${CVA6_REPO_DIR}/core/branch_unit.sv
${CVA6_REPO_DIR}/core/compressed_decoder.sv
${CVA6_REPO_DIR}/core/controller.sv
${CVA6_REPO_DIR}/core/csr_buffer.sv
${CVA6_REPO_DIR}/core/csr_regfile.sv
${CVA6_REPO_DIR}/core/decoder.sv
${CVA6_REPO_DIR}/core/ex_stage.sv
${CVA6_REPO_DIR}/core/instr_realign.sv
${CVA6_REPO_DIR}/core/id_stage.sv
${CVA6_REPO_DIR}/core/issue_read_operands.sv
${CVA6_REPO_DIR}/core/issue_stage.sv
${CVA6_REPO_DIR}/core/load_unit.sv
${CVA6_REPO_DIR}/core/load_store_unit.sv
${CVA6_REPO_DIR}/core/lsu_bypass.sv
${CVA6_REPO_DIR}/core/mult.sv
${CVA6_REPO_DIR}/core/multiplier.sv
${CVA6_REPO_DIR}/core/serdiv.sv
${CVA6_REPO_DIR}/core/perf_counters.sv
${CVA6_REPO_DIR}/core/ariane_regfile_ff.sv
${CVA6_REPO_DIR}/core/re_name.sv
// NOTE: scoreboard.sv modified for DSIM (unchanged for other simulators)
${CVA6_REPO_DIR}/core/scoreboard.sv
${CVA6_REPO_DIR}/core/store_buffer.sv
${CVA6_REPO_DIR}/core/amo_buffer.sv
${CVA6_REPO_DIR}/core/store_unit.sv
${CVA6_REPO_DIR}/core/commit_stage.sv
${CVA6_REPO_DIR}/core/axi_shim.sv
// What is "frontend"?
${CVA6_REPO_DIR}/core/frontend/btb.sv
${CVA6_REPO_DIR}/core/frontend/bht.sv
${CVA6_REPO_DIR}/core/frontend/ras.sv
${CVA6_REPO_DIR}/core/frontend/instr_scan.sv
${CVA6_REPO_DIR}/core/frontend/instr_queue.sv
${CVA6_REPO_DIR}/core/frontend/frontend.sv
// Cache subsystem
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_ctrl.sv
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_mem.sv
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_missunit.sv
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_wbuffer.sv
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache.sv
${CVA6_REPO_DIR}/core/cache_subsystem/cva6_icache.sv
${CVA6_REPO_DIR}/core/cache_subsystem/wt_cache_subsystem.sv
${CVA6_REPO_DIR}/core/cache_subsystem/wt_axi_adapter.sv
// Physical Memory Protection
// NOTE: pmp.sv modified for DSIM (unchanged for other simulators)
${CVA6_REPO_DIR}/core/pmp/src/pmp.sv
${CVA6_REPO_DIR}/core/pmp/src/pmp_entry.sv
// Tracer (behavioral code, not RTL)
${CVA6_REPO_DIR}/common/local/util/instr_tracer_if.sv
${CVA6_REPO_DIR}/common/local/util/instr_tracer.sv
${CVA6_REPO_DIR}/common/local/util/tc_sram_wrapper.sv
${CVA6_REPO_DIR}/corev_apu/src/tech_cells_generic/src/rtl/tc_sram.sv
${CVA6_REPO_DIR}/common/local/util/sram.sv
// MMU Sv32
${CVA6_REPO_DIR}/core/mmu_sv32/cva6_mmu_sv32.sv
${CVA6_REPO_DIR}/core/mmu_sv32/cva6_ptw_sv32.sv
${CVA6_REPO_DIR}/core/mmu_sv32/cva6_tlb_sv32.sv
// end of manifest

154
core/Flist.cv32a6_imac_sv32
View file

@ -1,154 +0,0 @@
//////////////////////////////////////////////////////////////////////////////
//
// Copyright 2021 OpenHW Group
//
// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// https://solderpad.org/licenses/
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
//
///////////////////////////////////////////////////////////////////////////////
//
// Manifest for the CVA6 CORE RTL model.
// - This is a CORE-ONLY manifest.
// - Relevent synthesis and simulation scripts/Makefiles must set the shell
// ENV variable CVA6_REPO_DIR.
//
///////////////////////////////////////////////////////////////////////////////
+define+WT_DCACHE
+incdir+${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/include/
+incdir+${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/
+incdir+${CVA6_REPO_DIR}/common/local/util/
${CVA6_REPO_DIR}/core/include/cv32a6_imac_sv0_config_pkg.sv
${CVA6_REPO_DIR}/core/include/riscv_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_dm_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_pkg.sv
// TODO: ariane_axi_pkg is dependent on this.
${CVA6_REPO_DIR}/corev_apu/axi/src/axi_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_rvfi_pkg.sv
// Packages
${CVA6_REPO_DIR}/core/include/ariane_axi_pkg.sv
${CVA6_REPO_DIR}/core/include/wt_cache_pkg.sv
${CVA6_REPO_DIR}/core/include/std_cache_pkg.sv
${CVA6_REPO_DIR}/core/include/axi_intf.sv
${CVA6_REPO_DIR}/core/include/instr_tracer_pkg.sv
//CVXIF
${CVA6_REPO_DIR}/core/include/cvxif_pkg.sv
${CVA6_REPO_DIR}/core/cvxif_fu.sv
// Common Cells
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/cf_math_pkg.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/fifo_v3.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/lfsr.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/lzc.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/shift_reg.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/unread.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/popcount.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/exp_backoff.sv
// Floating point unit
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_pkg.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_cast_multi.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_classifier.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_divsqrt_multi.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_fma_multi.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_fma.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_noncomp.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_opgroup_block.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_opgroup_fmt_slice.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_opgroup_multifmt_slice.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_rounding.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_top.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv
// Top-level source files (not necessarily instantiated at the top of the cva6).
${CVA6_REPO_DIR}/core/ariane.sv
${CVA6_REPO_DIR}/core/cva6.sv
${CVA6_REPO_DIR}/core/alu.sv
// Note: depends on fpnew_pkg, above
${CVA6_REPO_DIR}/core/fpu_wrap.sv
${CVA6_REPO_DIR}/core/branch_unit.sv
${CVA6_REPO_DIR}/core/compressed_decoder.sv
${CVA6_REPO_DIR}/core/controller.sv
${CVA6_REPO_DIR}/core/csr_buffer.sv
${CVA6_REPO_DIR}/core/csr_regfile.sv
${CVA6_REPO_DIR}/core/decoder.sv
${CVA6_REPO_DIR}/core/ex_stage.sv
${CVA6_REPO_DIR}/core/instr_realign.sv
${CVA6_REPO_DIR}/core/id_stage.sv
${CVA6_REPO_DIR}/core/issue_read_operands.sv
${CVA6_REPO_DIR}/core/issue_stage.sv
${CVA6_REPO_DIR}/core/load_unit.sv
${CVA6_REPO_DIR}/core/load_store_unit.sv
${CVA6_REPO_DIR}/core/lsu_bypass.sv
${CVA6_REPO_DIR}/core/mult.sv
${CVA6_REPO_DIR}/core/multiplier.sv
${CVA6_REPO_DIR}/core/serdiv.sv
${CVA6_REPO_DIR}/core/perf_counters.sv
${CVA6_REPO_DIR}/core/ariane_regfile_ff.sv
${CVA6_REPO_DIR}/core/re_name.sv
// NOTE: scoreboard.sv modified for DSIM (unchanged for other simulators)
${CVA6_REPO_DIR}/core/scoreboard.sv
${CVA6_REPO_DIR}/core/store_buffer.sv
${CVA6_REPO_DIR}/core/amo_buffer.sv
${CVA6_REPO_DIR}/core/store_unit.sv
${CVA6_REPO_DIR}/core/commit_stage.sv
${CVA6_REPO_DIR}/core/axi_shim.sv
// What is "frontend"?
${CVA6_REPO_DIR}/core/frontend/btb.sv
${CVA6_REPO_DIR}/core/frontend/bht.sv
${CVA6_REPO_DIR}/core/frontend/ras.sv
${CVA6_REPO_DIR}/core/frontend/instr_scan.sv
${CVA6_REPO_DIR}/core/frontend/instr_queue.sv
${CVA6_REPO_DIR}/core/frontend/frontend.sv
// Cache subsystem
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_ctrl.sv
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_mem.sv
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_missunit.sv
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_wbuffer.sv
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache.sv
${CVA6_REPO_DIR}/core/cache_subsystem/cva6_icache.sv
${CVA6_REPO_DIR}/core/cache_subsystem/wt_cache_subsystem.sv
${CVA6_REPO_DIR}/core/cache_subsystem/wt_axi_adapter.sv
// Physical Memory Protection
// NOTE: pmp.sv modified for DSIM (unchanged for other simulators)
${CVA6_REPO_DIR}/core/pmp/src/pmp.sv
${CVA6_REPO_DIR}/core/pmp/src/pmp_entry.sv
// Tracer (behavioral code, not RTL)
${CVA6_REPO_DIR}/common/local/util/instr_tracer_if.sv
${CVA6_REPO_DIR}/common/local/util/instr_tracer.sv
${CVA6_REPO_DIR}/common/local/util/tc_sram_wrapper.sv
${CVA6_REPO_DIR}/corev_apu/src/tech_cells_generic/src/rtl/tc_sram.sv
${CVA6_REPO_DIR}/common/local/util/sram.sv
// MMU Sv32
${CVA6_REPO_DIR}/core/mmu_sv32/cva6_mmu_sv32.sv
${CVA6_REPO_DIR}/core/mmu_sv32/cva6_ptw_sv32.sv
${CVA6_REPO_DIR}/core/mmu_sv32/cva6_tlb_sv32.sv
// end of manifest

154
core/Flist.cv32a6_imafc_sv32
View file

@ -1,154 +0,0 @@
//////////////////////////////////////////////////////////////////////////////
//
// Copyright 2021 OpenHW Group
//
// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// https://solderpad.org/licenses/
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
//
///////////////////////////////////////////////////////////////////////////////
//
// Manifest for the CVA6 CORE RTL model.
// - This is a CORE-ONLY manifest.
// - Relevent synthesis and simulation scripts/Makefiles must set the shell
// ENV variable CVA6_REPO_DIR.
//
///////////////////////////////////////////////////////////////////////////////
+define+WT_DCACHE
+incdir+${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/include/
+incdir+${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/
+incdir+${CVA6_REPO_DIR}/common/local/util/
${CVA6_REPO_DIR}/core/include/cv32a6_imac_sv0_config_pkg.sv
${CVA6_REPO_DIR}/core/include/riscv_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_dm_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_pkg.sv
// TODO: ariane_axi_pkg is dependent on this.
${CVA6_REPO_DIR}/corev_apu/axi/src/axi_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_rvfi_pkg.sv
// Packages
${CVA6_REPO_DIR}/core/include/ariane_axi_pkg.sv
${CVA6_REPO_DIR}/core/include/wt_cache_pkg.sv
${CVA6_REPO_DIR}/core/include/std_cache_pkg.sv
${CVA6_REPO_DIR}/core/include/axi_intf.sv
${CVA6_REPO_DIR}/core/include/instr_tracer_pkg.sv
//CVXIF
${CVA6_REPO_DIR}/core/include/cvxif_pkg.sv
${CVA6_REPO_DIR}/core/cvxif_fu.sv
// Common Cells
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/cf_math_pkg.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/fifo_v3.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/lfsr.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/lzc.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/shift_reg.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/unread.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/popcount.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/exp_backoff.sv
// Floating point unit
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_pkg.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_cast_multi.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_classifier.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_divsqrt_multi.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_fma_multi.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_fma.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_noncomp.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_opgroup_block.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_opgroup_fmt_slice.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_opgroup_multifmt_slice.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_rounding.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpnew_top.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv
${CVA6_REPO_DIR}/vendor/pulp-platform/fpnew/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv
// Top-level source files (not necessarily instantiated at the top of the cva6).
${CVA6_REPO_DIR}/core/ariane.sv
${CVA6_REPO_DIR}/core/cva6.sv
${CVA6_REPO_DIR}/core/alu.sv
// Note: depends on fpnew_pkg, above
${CVA6_REPO_DIR}/core/fpu_wrap.sv
${CVA6_REPO_DIR}/core/branch_unit.sv
${CVA6_REPO_DIR}/core/compressed_decoder.sv
${CVA6_REPO_DIR}/core/controller.sv
${CVA6_REPO_DIR}/core/csr_buffer.sv
${CVA6_REPO_DIR}/core/csr_regfile.sv
${CVA6_REPO_DIR}/core/decoder.sv
${CVA6_REPO_DIR}/core/ex_stage.sv
${CVA6_REPO_DIR}/core/instr_realign.sv
${CVA6_REPO_DIR}/core/id_stage.sv
${CVA6_REPO_DIR}/core/issue_read_operands.sv
${CVA6_REPO_DIR}/core/issue_stage.sv
${CVA6_REPO_DIR}/core/load_unit.sv
${CVA6_REPO_DIR}/core/load_store_unit.sv
${CVA6_REPO_DIR}/core/lsu_bypass.sv
${CVA6_REPO_DIR}/core/mult.sv
${CVA6_REPO_DIR}/core/multiplier.sv
${CVA6_REPO_DIR}/core/serdiv.sv
${CVA6_REPO_DIR}/core/perf_counters.sv
${CVA6_REPO_DIR}/core/ariane_regfile_ff.sv
${CVA6_REPO_DIR}/core/re_name.sv
// NOTE: scoreboard.sv modified for DSIM (unchanged for other simulators)
${CVA6_REPO_DIR}/core/scoreboard.sv
${CVA6_REPO_DIR}/core/store_buffer.sv
${CVA6_REPO_DIR}/core/amo_buffer.sv
${CVA6_REPO_DIR}/core/store_unit.sv
${CVA6_REPO_DIR}/core/commit_stage.sv
${CVA6_REPO_DIR}/core/axi_shim.sv
// What is "frontend"?
${CVA6_REPO_DIR}/core/frontend/btb.sv
${CVA6_REPO_DIR}/core/frontend/bht.sv
${CVA6_REPO_DIR}/core/frontend/ras.sv
${CVA6_REPO_DIR}/core/frontend/instr_scan.sv
${CVA6_REPO_DIR}/core/frontend/instr_queue.sv
${CVA6_REPO_DIR}/core/frontend/frontend.sv
// Cache subsystem
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_ctrl.sv
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_mem.sv
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_missunit.sv
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache_wbuffer.sv
${CVA6_REPO_DIR}/core/cache_subsystem/wt_dcache.sv
${CVA6_REPO_DIR}/core/cache_subsystem/cva6_icache.sv
${CVA6_REPO_DIR}/core/cache_subsystem/wt_cache_subsystem.sv
${CVA6_REPO_DIR}/core/cache_subsystem/wt_axi_adapter.sv
// Physical Memory Protection
// NOTE: pmp.sv modified for DSIM (unchanged for other simulators)
${CVA6_REPO_DIR}/core/pmp/src/pmp.sv
${CVA6_REPO_DIR}/core/pmp/src/pmp_entry.sv
// Tracer (behavioral code, not RTL)
${CVA6_REPO_DIR}/common/local/util/instr_tracer_if.sv
${CVA6_REPO_DIR}/common/local/util/instr_tracer.sv
${CVA6_REPO_DIR}/common/local/util/tc_sram_wrapper.sv
${CVA6_REPO_DIR}/corev_apu/src/tech_cells_generic/src/rtl/tc_sram.sv
${CVA6_REPO_DIR}/common/local/util/sram.sv
// MMU Sv32
${CVA6_REPO_DIR}/core/mmu_sv32/cva6_mmu_sv32.sv
${CVA6_REPO_DIR}/core/mmu_sv32/cva6_ptw_sv32.sv
${CVA6_REPO_DIR}/core/mmu_sv32/cva6_tlb_sv32.sv
// end of manifest

33
core/Flist.cv64a6_imafdc_sv39_gate
View file

@ -1,33 +0,0 @@
# Copyright 2021 Thales DIS design services SAS
#
# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
# You may obtain a copy of the License at https://solderpad.org/licenses/
#
# Original Author: Jean-Roch COULON (jean-roch.coulon@thalesgroup.com)
#
${CVA6_REPO_DIR}/core/include/cv64a6_imafdc_sv39_config_pkg.sv
${CVA6_REPO_DIR}/core/include/riscv_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_dm_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_pkg.sv
// TODO: ariane_axi_pkg is dependent on this.
${CVA6_REPO_DIR}/corev_apu/axi/src/axi_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_rvfi_pkg.sv
${CVA6_REPO_DIR}/core/include/cvxif_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_axi_pkg.sv
${CVA6_REPO_DIR}/core/include/wt_cache_pkg.sv
${CVA6_REPO_DIR}/core/include/std_cache_pkg.sv
${CVA6_REPO_DIR}/core/include/axi_intf.sv
${CVA6_REPO_DIR}/core/include/instr_tracer_pkg.sv
${LIB_VERILOG}
${CVA6_REPO_DIR}/pd/synth/cva6_cv64a6_imafdc_sv39_synth_modified.v
${CVA6_REPO_DIR}/pd/synth/tc_sram_wrapper_256_64_00000008_00000001_00000001_none_0.sv
${CVA6_REPO_DIR}/common/local/util/tc_sram_wrapper.sv
${CVA6_REPO_DIR}/corev_apu/src/tech_cells_generic/src/rtl/tc_sram.sv
${CVA6_REPO_DIR}/common/local/util/sram.sv

7
core/Flist.cv64a6_imafdc_sv39 → core/Flist.cva6
View file

@ -31,7 +31,7 @@
+incdir+${CVA6_REPO_DIR}/vendor/pulp-platform/common_cells/src/
+incdir+${CVA6_REPO_DIR}/common/local/util/
${CVA6_REPO_DIR}/core/include/cv64a6_imafdc_sv39_config_pkg.sv
${CVA6_REPO_DIR}/core/include/${TARGET_CFG}_config_pkg.sv
${CVA6_REPO_DIR}/core/include/riscv_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_dm_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_pkg.sv
@ -158,4 +158,9 @@ ${CVA6_REPO_DIR}/core/mmu_sv39/mmu.sv
${CVA6_REPO_DIR}/core/mmu_sv39/ptw.sv
${CVA6_REPO_DIR}/core/mmu_sv39/tlb.sv
// MMU Sv32
${CVA6_REPO_DIR}/core/mmu_sv32/cva6_mmu_sv32.sv
${CVA6_REPO_DIR}/core/mmu_sv32/cva6_ptw_sv32.sv
${CVA6_REPO_DIR}/core/mmu_sv32/cva6_tlb_sv32.sv
// end of manifest

5
core/Flist.cv32a60x_gate → core/Flist.cva6_gate
View file

@ -8,7 +8,7 @@
# Original Author: Jean-Roch COULON (jean-roch.coulon@thalesgroup.com)
#
${CVA6_REPO_DIR}/core/include/cv32a60x_config_pkg.sv
${CVA6_REPO_DIR}/core/include/${TARGET_CFG}_config_pkg.sv
${CVA6_REPO_DIR}/core/include/riscv_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_dm_pkg.sv
${CVA6_REPO_DIR}/core/include/ariane_pkg.sv
@ -24,9 +24,8 @@ ${CVA6_REPO_DIR}/core/include/std_cache_pkg.sv
${CVA6_REPO_DIR}/core/include/axi_intf.sv
${CVA6_REPO_DIR}/core/include/instr_tracer_pkg.sv
# NETLIST
${LIB_VERILOG}
${CVA6_REPO_DIR}/pd/synth/cva6_cv32a60x_synth_modified.v
${CVA6_REPO_DIR}/pd/synth/cva6_${TARGET_CFG}_synth_modified.v
${CVA6_REPO_DIR}/pd/synth/tc_sram_wrapper_256_64_00000008_00000001_00000001_none_0.sv
${CVA6_REPO_DIR}/common/local/util/tc_sram_wrapper.sv

2
pd/synth/Makefile
View file

@ -29,7 +29,7 @@ ifndef TECH_NAME
endif
pre_cva6_synth:
grep "CVA6_REPO_DIR\}" ../../core/Flist.$(TARGET)|grep -v "instr_tracer"|grep -v "incdir" > Flist.cva6_synth
grep "CVA6_REPO_DIR\}" ../../core/Flist.cva6|grep -v "instr_tracer"|grep -v "incdir" > Flist.cva6_synth
sed -i "s/^/analyze -f sverilog -define {WT_DCACHE,RVFI_TRACE} -lib ariane_lib /" Flist.cva6_synth
cva6_synth: pre_cva6_synth

1
pd/synth/cva6_synth.tcl
View file

@ -24,6 +24,7 @@ sh mkdir work
define_design_lib ariane_lib -path work
set CVA6_REPO_DIR "../../"
set TARGET_CFG $TARGET
source Flist.cva6_synth
elaborate ${DESIGN_NAME} -library ariane_lib