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📝 Update documentation with CSR FU

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Florian Zaruba 2017-05-05 11:28:55 +02:00
parent 9ea677b843
commit 4b75332d10
4 changed files with 7323 additions and 7116 deletions
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@ -8,4 +8,11 @@ By widening the fetch interface to 64bit we could theoretically fetch two and mo
The CSR’s APB interface would allow for storing the CPU state (registers, CSR registers, etc.) to a state retentive memory when the core is in complete power down.
## Input silencing of ALU
## Input silencing of ALU
## Performance counters
- Miss-predicts
- Mem Arbiter full
- Store Queue full
- Scoreboard full