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Fix CHANGELOG.md
to point to the right versions
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@ -23,7 +23,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
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- Fix VCS elab warning in `load_store_unit`
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- Replace PLIC with implementation from lowRISC
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- Re-work interrupt and debug subsystem to associate requests during decode. This improves stability on for non-idempotent loads.
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- Several submodules have been updated: `common_cells` to `v1.13.0`, `riscv-dbg` to `v0.1`, `fpnew` to `v0.5.3` and `axi` to `v0.7.0`
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- Several submodules have been updated: `common_cells` to `v1.13.1`, `riscv-dbg` to `v0.1`, `fpnew` to `v0.5.5` and `axi` to `v0.7.0`
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- Improve FPU pipelining and timing around scoreboard
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- Reworked the `axilite` to PLIC shim for OpenPiton+Ariane
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- Remove `in` and `out` aliases for AXI interfaces
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@ -31,7 +31,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
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- Fix wrong dirtying of `sd` flag in `mstatus`
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- Synthesis fix for `Vivado 2018.3`
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- Clean-up instruction front-end, small IPC improvement
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- Move to Verilator 4.014
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- Move to Verilator `4.014`
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### 4.1.2
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