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https://github.com/openhwgroup/cva6.git
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utils.py: format and fix typos (#2163)
This commit is contained in:
André Sintzoff
GitHub
parent
b6495684ba
commit
4df326e13c
1 changed files with 69 additions and 45 deletions
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@ -30,10 +30,12 @@ from libs.isa_updater import isa_filter
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from libs.csr_updater import csr_formatter
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from libs.csr_factorizer import factorizer
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pattern_warl = r"\b(?:warl|wlrl|ro_constant|ro_variable)\b" #pattern to detect warl in field
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pattern_legal_dict = r"\[(0x[0-9A-Fa-f]+)(.*?(0x[0-9A-Fa-f]+))?\]" # pattern to detect if warl field is dict
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pattern_legal_list = r"\[(0x[0-9A-Fa-f]+)(.*?(0x[0-9A-Fa-f]+))?\]" #pattern to detect if warl field is a list
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Factorizer_pattern = r".*(\d).*" # pattern to detect factorized fields
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pattern_warl = (
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r"\b(?:warl|wlrl|ro_constant|ro_variable)\b" # pattern to detect warl in field
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)
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pattern_legal_dict = r"\[(0x[0-9A-Fa-f]+)(.*?(0x[0-9A-Fa-f]+))?\]" # pattern to detect if warl field is dict
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pattern_legal_list = r"\[(0x[0-9A-Fa-f]+)(.*?(0x[0-9A-Fa-f]+))?\]" # pattern to detect if warl field is a list
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Factorizer_pattern = r".*(\d).*" # pattern to detect factorized fields
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class DocumentClass:
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@ -75,7 +77,7 @@ class AddressBlockClass:
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def returnAsString(self):
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raise NotImplementedError(
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"method returnAsString() is virutal and must be overridden."
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"method returnAsString() is virtual and must be overridden."
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)
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@ -180,7 +182,7 @@ class InstructionBlockClass:
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def returnAsString(self):
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raise NotImplementedError(
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"method returnAsString() is virutal and must be overridden."
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"method returnAsString() is virtual and must be overridden."
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)
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@ -208,10 +210,15 @@ class RstAddressBlock(AddressBlockClass):
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regDescrList = [reg.desc for reg in registerlist]
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regRV32List = [reg.RV32 for reg in registerlist]
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regRV64List = [reg.RV64 for reg in registerlist]
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r.directive('..', content= ["Copyright (c) 2024 OpenHW Group",
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"Copyright (c) 2024 Thales",
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"SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1",
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"Author: Abdessamii Oukalrazqou"])
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r.directive(
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"..",
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content=[
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"Copyright (c) 2024 OpenHW Group",
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"Copyright (c) 2024 Thales",
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"SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1",
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"Author: Abdessamii Oukalrazqou",
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],
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)
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r.title(self.name) # Use the name of the addressBlock as title
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r.newline()
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r.h2("Register Summary")
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@ -236,7 +243,7 @@ class RstAddressBlock(AddressBlockClass):
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"Reset Value",
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"0x" + f"{reg.resetValue[2:].zfill(int(reg.size/4))}",
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)
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r.field("priviliege mode", reg.access)
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r.field("Privilege Mode", reg.access)
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r.field("Description", reg.desc)
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for field in reg.field:
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if field.bitWidth == 1: # only one bit -> no range needed
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@ -252,7 +259,7 @@ class RstAddressBlock(AddressBlockClass):
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]
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_line.append(field.fieldDesc)
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reg_table.append(_line)
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_headers = ["Bits", "Field name", "Legalvalues", "Mask", "Access"]
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_headers = ["Bits", "Field Name", "Legal Values", "Mask", "Access"]
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_headers.append("Description")
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# table of the register
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r.table(header=_headers, data=reg_table)
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@ -260,7 +267,7 @@ class RstAddressBlock(AddressBlockClass):
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class InstrstBlock(InstructionBlockClass):
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"""Generates a ISA ReStructuredText file from RISC V Config Yaml register description"""
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"""Generates a ISA ReStructuredText file from RISC-V Config Yaml register description"""
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def __init__(self, name):
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super().__init__("isa")
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@ -275,10 +282,15 @@ class InstrstBlock(InstructionBlockClass):
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InstrNameList = [reg.key for reg in self.Instructionlist]
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InstrDescrList = [reg.descr for reg in self.Instructionlist]
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InstrExtList = [reg.Extension_Name for reg in self.Instructionlist]
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r.directive('..', content= ["Copyright (c) 2024 OpenHW Group",
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"Copyright (c) 2024 Thales",
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"SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1",
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"Author: Abdessamii Oukalrazqou"])
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r.directive(
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"..",
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content=[
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"Copyright (c) 2024 OpenHW Group",
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"Copyright (c) 2024 Thales",
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"SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1",
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"Author: Abdessamii Oukalrazqou",
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],
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)
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r.title(self.name) # Use the name of the addressBlock as title
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r.newline()
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r.h2("Instructions")
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@ -291,15 +303,15 @@ class InstrstBlock(InstructionBlockClass):
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str(InstrDescrList[i]),
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]
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)
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r.table(header=["Subset Name", "Name ", "Description"], data=summary_table)
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r.table(header=["Subset Name", "Name", "Description"], data=summary_table)
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for reg in self.Instructionlist:
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reg_table = []
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_headers = [
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"Name",
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"Format",
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"pseudocode",
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"invalid_values",
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"exception_raised",
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"Pseudocode",
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"Invalid_values",
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"Exception_raised",
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"Description",
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"Op Name",
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]
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@ -336,9 +348,15 @@ class InstmdBlock(InstructionBlockClass):
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InstrNameList = [reg.key for reg in self.Instructionlist]
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InstrDescrList = [reg.descr for reg in self.Instructionlist]
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InstrExtList = [reg.Extension_Name for reg in self.Instructionlist]
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licence = ["<!--Copyright (c) 2024 OpenHW Group","Copyright (c) 2024 Thales","SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 ","Author: Abdessamii Oukalrazqou" ,"-->"]
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for l in licence :
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self.mdFile.write(l + '\n')
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licence = [
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"<!--Copyright (c) 2024 OpenHW Group",
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"Copyright (c) 2024 Thales",
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"SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 ",
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"Author: Abdessamii Oukalrazqou",
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"-->",
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]
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for l in licence:
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self.mdFile.write(l + "\n")
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self.mdFile.new_header(
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level=1, title=self.name
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) # Use the name of the addressBlock as title
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@ -425,9 +443,15 @@ class MdAddressBlock(AddressBlockClass):
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regNameList = [reg.name for reg in registerlist if reg.RV32 | reg.RV64]
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regAddressList = [reg.address for reg in registerlist if reg.RV32 | reg.RV64]
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regDescrList = [reg.desc for reg in registerlist if reg.RV32 | reg.RV64]
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licence = ["<!--Copyright (c) 2024 OpenHW Group","Copyright (c) 2024 Thales","SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 ","Author: Abdessamii Oukalrazqou" ,"-->"]
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for l in licence :
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self.mdFile.write(l + '\n')
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licence = [
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"<!--Copyright (c) 2024 OpenHW Group",
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"Copyright (c) 2024 Thales",
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"SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 ",
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"Author: Abdessamii Oukalrazqou",
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"-->",
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]
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for l in licence:
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self.mdFile.write(l + "\n")
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self.mdFile.new_header(
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level=1, title=self.name
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) # Use the name of the addressBlock as title
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@ -455,7 +479,7 @@ class MdAddressBlock(AddressBlockClass):
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self.mdFile.new_header(level=3, title="Registers Description")
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for reg in registerlist:
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if reg.RV64 | reg.RV32:
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headers = ["Bits", "Field name", "legal values", "Mask", "Access"]
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headers = ["Bits", "Field Name", "Legal Values", "Mask", "Access"]
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headers.append("Description")
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self.returnMdRegDesc(
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reg.name, reg.address, reg.resetValue, reg.desc, reg.access
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@ -487,14 +511,14 @@ class MdAddressBlock(AddressBlockClass):
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self.mdFile.new_line("**Address** " + str(address))
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if resetValue:
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# display the resetvalue in hex notation in the full length of the register
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self.mdFile.new_line("**Reset Value**" + resetValue)
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self.mdFile.new_line("**Priviliege mode** " + access)
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self.mdFile.new_line("**Reset Value** " + resetValue)
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self.mdFile.new_line("**Privilege Mode** " + access)
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self.mdFile.new_line("**Description** " + desc)
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# -----------------------------------------------------------------------------------------------------------------------#
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class CsrParser:
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"""parse CSR risc-v config yaml file"""
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"""parse CSR RISC-V config yaml file"""
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def __init__(self, srcFile, target, modiFile=None):
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self.srcFile = srcFile
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@ -578,11 +602,11 @@ class CsrParser:
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match_field = re.search(Factorizer_pattern, str(item))
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if match_field:
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fieldName = re.sub(
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match_field.group(1),
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f"[i*4 + {match_field.group(1)}]",
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item,
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)
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else :
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match_field.group(1),
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f"[i*4 + {match_field.group(1)}]",
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item,
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)
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else:
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fieldName = item
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elif isinstance(item, list):
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for item_ in item:
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@ -596,15 +620,15 @@ class CsrParser:
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bitlegal = legal
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bitmask = ""
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f = Field(
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fieldName,
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bitlegal,
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bitmask,
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bitmsb,
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bitlsb,
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bitWidth,
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fieldDesc,
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fieldaccess,
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)
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fieldName,
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bitlegal,
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bitmask,
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bitmsb,
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bitlsb,
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bitWidth,
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fieldDesc,
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fieldaccess,
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)
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field.append(f)
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elif len(fieldList) == 0:
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pattern = r"(\D+)\[(\d+)\-\d+\](.*)"
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