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superscalar: make SuperscalarEn a CVA6Cfg attribute (#2322)

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Côme 2024-07-05 14:09:48 +02:00 • committed by GitHub
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29 changed files with 330 additions and 338 deletions
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50
core/cva6.sv
View file

@ -354,29 +354,29 @@ module cva6
// --------------
// IF <-> ID
// --------------
fetch_entry_t [ariane_pkg::SUPERSCALAR:0] fetch_entry_if_id;
logic [ariane_pkg::SUPERSCALAR:0] fetch_valid_if_id;
logic [ariane_pkg::SUPERSCALAR:0] fetch_ready_id_if;
fetch_entry_t [CVA6Cfg.NrIssuePorts-1:0] fetch_entry_if_id;
logic [CVA6Cfg.NrIssuePorts-1:0] fetch_valid_if_id;
logic [CVA6Cfg.NrIssuePorts-1:0] fetch_ready_id_if;
// --------------
// ID <-> ISSUE
// --------------
scoreboard_entry_t [ariane_pkg::SUPERSCALAR:0] issue_entry_id_issue;
logic [ariane_pkg::SUPERSCALAR:0][31:0] orig_instr_id_issue;
logic [ariane_pkg::SUPERSCALAR:0] issue_entry_valid_id_issue;
logic [ariane_pkg::SUPERSCALAR:0] is_ctrl_fow_id_issue;
logic [ariane_pkg::SUPERSCALAR:0] issue_instr_issue_id;
scoreboard_entry_t [CVA6Cfg.NrIssuePorts-1:0] issue_entry_id_issue;
logic [CVA6Cfg.NrIssuePorts-1:0][31:0] orig_instr_id_issue;
logic [CVA6Cfg.NrIssuePorts-1:0] issue_entry_valid_id_issue;
logic [CVA6Cfg.NrIssuePorts-1:0] is_ctrl_fow_id_issue;
logic [CVA6Cfg.NrIssuePorts-1:0] issue_instr_issue_id;
// --------------
// ISSUE <-> EX
// --------------
logic [SUPERSCALAR:0][CVA6Cfg.VLEN-1:0] rs1_forwarding_id_ex; // unregistered version of fu_data_o.operanda
logic [SUPERSCALAR:0][CVA6Cfg.VLEN-1:0] rs2_forwarding_id_ex; // unregistered version of fu_data_o.operandb
logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.VLEN-1:0] rs1_forwarding_id_ex; // unregistered version of fu_data_o.operanda
logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.VLEN-1:0] rs2_forwarding_id_ex; // unregistered version of fu_data_o.operandb
fu_data_t [SUPERSCALAR:0] fu_data_id_ex;
fu_data_t [CVA6Cfg.NrIssuePorts-1:0] fu_data_id_ex;
logic [CVA6Cfg.VLEN-1:0] pc_id_ex;
logic is_compressed_instr_id_ex;
logic [SUPERSCALAR:0][31:0] tinst_ex;
logic [CVA6Cfg.NrIssuePorts-1:0][31:0] tinst_ex;
// fixed latency units
logic flu_ready_ex_id;
logic [CVA6Cfg.TRANS_ID_BITS-1:0] flu_trans_id_ex_id;
@ -384,14 +384,14 @@ module cva6
logic [CVA6Cfg.XLEN-1:0] flu_result_ex_id;
exception_t flu_exception_ex_id;
// ALU
logic [SUPERSCALAR:0] alu_valid_id_ex;
logic [CVA6Cfg.NrIssuePorts-1:0] alu_valid_id_ex;
// Branches and Jumps
logic [SUPERSCALAR:0] branch_valid_id_ex;
logic [CVA6Cfg.NrIssuePorts-1:0] branch_valid_id_ex;
branchpredict_sbe_t branch_predict_id_ex;
logic resolve_branch_ex_id;
// LSU
logic [SUPERSCALAR:0] lsu_valid_id_ex;
logic [CVA6Cfg.NrIssuePorts-1:0] lsu_valid_id_ex;
logic lsu_ready_ex_id;
logic [CVA6Cfg.TRANS_ID_BITS-1:0] load_trans_id_ex_id;
@ -404,10 +404,10 @@ module cva6
logic store_valid_ex_id;
exception_t store_exception_ex_id;
// MULT
logic [SUPERSCALAR:0] mult_valid_id_ex;
logic [CVA6Cfg.NrIssuePorts-1:0] mult_valid_id_ex;
// FPU
logic fpu_ready_ex_id;
logic [SUPERSCALAR:0] fpu_valid_id_ex;
logic [CVA6Cfg.NrIssuePorts-1:0] fpu_valid_id_ex;
logic [1:0] fpu_fmt_id_ex;
logic [2:0] fpu_rm_id_ex;
logic [CVA6Cfg.TRANS_ID_BITS-1:0] fpu_trans_id_ex_id;
@ -415,7 +415,7 @@ module cva6
logic fpu_valid_ex_id;
exception_t fpu_exception_ex_id;
// ALU2
logic [SUPERSCALAR:0] alu2_valid_id_ex;
logic [CVA6Cfg.NrIssuePorts-1:0] alu2_valid_id_ex;
// Accelerator
logic stall_acc_id;
scoreboard_entry_t issue_instr_id_acc;
@ -429,7 +429,7 @@ module cva6
logic acc_resp_fflags_valid;
logic single_step_acc_commit;
// CSR
logic [SUPERSCALAR:0] csr_valid_id_ex;
logic [CVA6Cfg.NrIssuePorts-1:0] csr_valid_id_ex;
logic csr_hs_ld_st_inst_ex;
// CVXIF
logic [CVA6Cfg.TRANS_ID_BITS-1:0] x_trans_id_ex_id;
@ -437,7 +437,7 @@ module cva6
logic x_valid_ex_id;
exception_t x_exception_ex_id;
logic x_we_ex_id;
logic [SUPERSCALAR:0] x_issue_valid_id_ex;
logic [CVA6Cfg.NrIssuePorts-1:0] x_issue_valid_id_ex;
logic x_issue_ready_ex_id;
logic [31:0] x_off_instr_id_ex;
// --------------
@ -467,7 +467,7 @@ module cva6
// --------------
// RVFI
// --------------
logic [ariane_pkg::SUPERSCALAR:0][CVA6Cfg.TRANS_ID_BITS-1:0] rvfi_issue_pointer;
logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] rvfi_issue_pointer;
logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] rvfi_commit_pointer;
// --------------
// COMMIT <-> ID
@ -583,7 +583,7 @@ module cva6
//RVFI
lsu_ctrl_t rvfi_lsu_ctrl;
logic [CVA6Cfg.PLEN-1:0] rvfi_mem_paddr;
logic [ariane_pkg::SUPERSCALAR:0] rvfi_is_compressed;
logic [CVA6Cfg.NrIssuePorts-1:0] rvfi_is_compressed;
rvfi_probes_csr_t rvfi_csr;
// Accelerator port
@ -1591,8 +1591,8 @@ module cva6
//RVFI INSTR
logic [ariane_pkg::SUPERSCALAR:0][31:0] rvfi_fetch_instr;
for (genvar i = 0; i <= ariane_pkg::SUPERSCALAR; i++) begin
logic [CVA6Cfg.NrIssuePorts-1:0][31:0] rvfi_fetch_instr;
for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
assign rvfi_fetch_instr[i] = fetch_entry_if_id[i].instruction;
end
@ -1642,7 +1642,7 @@ module cva6
//pragma translate_off
initial begin
assert (!(ariane_pkg::SUPERSCALAR && CVA6Cfg.EnableAccelerator))
assert (!(CVA6Cfg.SuperscalarEn && CVA6Cfg.EnableAccelerator))
else $fatal(1, "Accelerator is not supported by superscalar pipeline");
end
//pragma translate_on

50
core/cva6_rvfi.sv
View file

@ -51,21 +51,21 @@ module cva6_rvfi
localparam logic [63:0] SMODE_STATUS_READ_MASK = ariane_pkg::smode_status_read_mask(CVA6Cfg);
logic flush;
logic [ariane_pkg::SUPERSCALAR:0] issue_instr_ack;
logic [ariane_pkg::SUPERSCALAR:0] fetch_entry_valid;
logic [ariane_pkg::SUPERSCALAR:0][31:0] instruction;
logic [ariane_pkg::SUPERSCALAR:0] is_compressed;
logic [ariane_pkg::SUPERSCALAR:0][31:0] truncated;
logic [CVA6Cfg.NrIssuePorts-1:0] issue_instr_ack;
logic [CVA6Cfg.NrIssuePorts-1:0] fetch_entry_valid;
logic [CVA6Cfg.NrIssuePorts-1:0][31:0] instruction;
logic [CVA6Cfg.NrIssuePorts-1:0] is_compressed;
logic [CVA6Cfg.NrIssuePorts-1:0][31:0] truncated;
logic [ariane_pkg::SUPERSCALAR:0][CVA6Cfg.TRANS_ID_BITS-1:0] issue_pointer;
logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] issue_pointer;
logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] commit_pointer;
logic flush_unissued_instr;
logic [ariane_pkg::SUPERSCALAR:0] decoded_instr_valid;
logic [ariane_pkg::SUPERSCALAR:0] decoded_instr_ack;
logic [CVA6Cfg.NrIssuePorts-1:0] decoded_instr_valid;
logic [CVA6Cfg.NrIssuePorts-1:0] decoded_instr_ack;
logic [ariane_pkg::SUPERSCALAR:0][CVA6Cfg.XLEN-1:0] rs1_forwarding;
logic [ariane_pkg::SUPERSCALAR:0][CVA6Cfg.XLEN-1:0] rs2_forwarding;
logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rs1_forwarding;
logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rs2_forwarding;
logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.VLEN-1:0] commit_instr_pc;
fu_op [CVA6Cfg.NrCommitPorts-1:0] commit_instr_op;
@ -161,7 +161,7 @@ module cva6_rvfi
//ID STAGE
for (genvar i = 0; i <= ariane_pkg::SUPERSCALAR; i++) begin
for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
assign truncated[i] = (is_compressed[i]) ? {16'b0, instruction[i][15:0]} : instruction[i];
end
@ -169,42 +169,42 @@ module cva6_rvfi
logic valid;
logic [31:0] instr;
} issue_struct_t;
issue_struct_t [ariane_pkg::SUPERSCALAR:0] issue_n, issue_q;
issue_struct_t [CVA6Cfg.NrIssuePorts-1:0] issue_n, issue_q;
logic took0;
always_comb begin
issue_n = issue_q;
took0 = 1'b0;
for (int unsigned i = 0; i <= ariane_pkg::SUPERSCALAR; i++) begin
for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
if (issue_instr_ack[i]) begin
issue_n[i].valid = 1'b0;
end
end
if (!issue_n[ariane_pkg::SUPERSCALAR].valid) begin
issue_n[ariane_pkg::SUPERSCALAR].valid = fetch_entry_valid[0];
issue_n[ariane_pkg::SUPERSCALAR].instr = truncated[0];
if (!issue_n[CVA6Cfg.NrIssuePorts-1].valid) begin
issue_n[CVA6Cfg.NrIssuePorts-1].valid = fetch_entry_valid[0];
issue_n[CVA6Cfg.NrIssuePorts-1].instr = truncated[0];
took0 = 1'b1;
end
if (!issue_n[0].valid) begin
issue_n[0] = issue_n[ariane_pkg::SUPERSCALAR];
issue_n[ariane_pkg::SUPERSCALAR].valid = 1'b0;
issue_n[0] = issue_n[CVA6Cfg.NrIssuePorts-1];
issue_n[CVA6Cfg.NrIssuePorts-1].valid = 1'b0;
end
if (!issue_n[ariane_pkg::SUPERSCALAR].valid) begin
if (!issue_n[CVA6Cfg.NrIssuePorts-1].valid) begin
if (took0) begin
issue_n[ariane_pkg::SUPERSCALAR].valid = fetch_entry_valid[ariane_pkg::SUPERSCALAR];
issue_n[ariane_pkg::SUPERSCALAR].instr = truncated[ariane_pkg::SUPERSCALAR];
issue_n[CVA6Cfg.NrIssuePorts-1].valid = fetch_entry_valid[CVA6Cfg.NrIssuePorts-1];
issue_n[CVA6Cfg.NrIssuePorts-1].instr = truncated[CVA6Cfg.NrIssuePorts-1];
end else begin
issue_n[ariane_pkg::SUPERSCALAR].valid = fetch_entry_valid[0];
issue_n[ariane_pkg::SUPERSCALAR].instr = truncated[0];
issue_n[CVA6Cfg.NrIssuePorts-1].valid = fetch_entry_valid[0];
issue_n[CVA6Cfg.NrIssuePorts-1].instr = truncated[0];
end
end
if (flush) begin
for (int unsigned i = 0; i <= ariane_pkg::SUPERSCALAR; i++) begin
for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
issue_n[i].valid = 1'b0;
end
end
@ -235,7 +235,7 @@ module cva6_rvfi
always_comb begin : issue_fifo
mem_n = mem_q;
for (int unsigned i = 0; i <= ariane_pkg::SUPERSCALAR; i++) begin
for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
if (decoded_instr_valid[i] && decoded_instr_ack[i] && !flush_unissued_instr) begin
mem_n[issue_pointer[i]] = '{
rs1_rdata: rs1_forwarding[i],

22
core/cva6_rvfi_probes.sv
View file

@ -22,21 +22,21 @@ module cva6_rvfi_probes
) (
input logic flush_i,
input logic [SUPERSCALAR:0] issue_instr_ack_i,
input logic [SUPERSCALAR:0] fetch_entry_valid_i,
input logic [SUPERSCALAR:0][31:0] instruction_i,
input logic [SUPERSCALAR:0] is_compressed_i,
input logic flush_i,
input logic [CVA6Cfg.NrIssuePorts-1:0] issue_instr_ack_i,
input logic [CVA6Cfg.NrIssuePorts-1:0] fetch_entry_valid_i,
input logic [CVA6Cfg.NrIssuePorts-1:0][31:0] instruction_i,
input logic [CVA6Cfg.NrIssuePorts-1:0] is_compressed_i,
input logic [ SUPERSCALAR : 0][CVA6Cfg.TRANS_ID_BITS-1:0] issue_pointer_i,
input logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] commit_pointer_i,
input logic [CVA6Cfg.NrIssuePorts-1 : 0][CVA6Cfg.TRANS_ID_BITS-1:0] issue_pointer_i,
input logic [ CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] commit_pointer_i,
input logic flush_unissued_instr_i,
input logic [SUPERSCALAR:0] decoded_instr_valid_i,
input logic [SUPERSCALAR:0] decoded_instr_ack_i,
input logic [CVA6Cfg.NrIssuePorts-1:0] decoded_instr_valid_i,
input logic [CVA6Cfg.NrIssuePorts-1:0] decoded_instr_ack_i,
input logic [SUPERSCALAR:0][CVA6Cfg.VLEN-1:0] rs1_forwarding_i,
input logic [SUPERSCALAR:0][CVA6Cfg.VLEN-1:0] rs2_forwarding_i,
input logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.VLEN-1:0] rs1_forwarding_i,
input logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.VLEN-1:0] rs2_forwarding_i,
input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i,
input logic [CVA6Cfg.NrCommitPorts-1:0] commit_drop_i,

40
core/ex_stage.sv
View file

@ -39,17 +39,17 @@ module ex_stage
// Debug mode is enabled - CSR_REGFILE
input logic debug_mode_i,
// rs1 forwarding - ISSUE_STAGE
input logic [SUPERSCALAR:0][CVA6Cfg.VLEN-1:0] rs1_forwarding_i,
input logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.VLEN-1:0] rs1_forwarding_i,
// rs2 forwarding - ISSUE_STAGE
input logic [SUPERSCALAR:0][CVA6Cfg.VLEN-1:0] rs2_forwarding_i,
input logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.VLEN-1:0] rs2_forwarding_i,
// FU data useful to execute instruction - ISSUE_STAGE
input fu_data_t [SUPERSCALAR:0] fu_data_i,
input fu_data_t [CVA6Cfg.NrIssuePorts-1:0] fu_data_i,
// PC of the current instruction - ISSUE_STAGE
input logic [CVA6Cfg.VLEN-1:0] pc_i,
// Report whether instruction is compressed - ISSUE_STAGE
input logic is_compressed_instr_i,
// Report instruction encoding - ISSUE_STAGE
input logic [SUPERSCALAR:0][31:0] tinst_i,
input logic [CVA6Cfg.NrIssuePorts-1:0][31:0] tinst_i,
// Fixed Latency Unit result - ISSUE_STAGE
output logic [CVA6Cfg.XLEN-1:0] flu_result_o,
// ID of the scoreboard entry at which a=to write back - ISSUE_STAGE
@ -61,9 +61,9 @@ module ex_stage
// FLU result is valid - ISSUE_STAGE
output logic flu_valid_o,
// ALU instruction is valid - ISSUE_STAGE
input logic [SUPERSCALAR:0] alu_valid_i,
input logic [CVA6Cfg.NrIssuePorts-1:0] alu_valid_i,
// Branch unit instruction is valid - ISSUE_STAGE
input logic [SUPERSCALAR:0] branch_valid_i,
input logic [CVA6Cfg.NrIssuePorts-1:0] branch_valid_i,
// Information of branch prediction - ISSUE_STAGE
input branchpredict_sbe_t branch_predict_i,
// The branch engine uses the write back from the ALU - several_modules
@ -71,17 +71,17 @@ module ex_stage
// Signaling that we resolved the branch - ISSUE_STAGE
output logic resolve_branch_o,
// CSR instruction is valid - ISSUE_STAGE
input logic [SUPERSCALAR:0] csr_valid_i,
input logic [CVA6Cfg.NrIssuePorts-1:0] csr_valid_i,
// CSR address to write - COMMIT_STAGE
output logic [11:0] csr_addr_o,
// CSR commit - COMMIT_STAGE
input logic csr_commit_i,
// MULT instruction is valid - ISSUE_STAGE
input logic [SUPERSCALAR:0] mult_valid_i,
input logic [CVA6Cfg.NrIssuePorts-1:0] mult_valid_i,
// LSU is ready - ISSUE_STAGE
output logic lsu_ready_o,
// LSU instruction is valid - ISSUE_STAGE
input logic [SUPERSCALAR:0] lsu_valid_i,
input logic [CVA6Cfg.NrIssuePorts-1:0] lsu_valid_i,
// Load result is valid - ISSUE_STAGE
output logic load_valid_o,
// Load result valid - ISSUE_STAGE
@ -113,7 +113,7 @@ module ex_stage
// FU is ready - ISSUE_STAGE
output logic fpu_ready_o,
// FPU instruction is ready - ISSUE_STAGE
input logic [SUPERSCALAR:0] fpu_valid_i,
input logic [CVA6Cfg.NrIssuePorts-1:0] fpu_valid_i,
// FPU format - ISSUE_STAGE
input logic [1:0] fpu_fmt_i,
// FPU rm - ISSUE_STAGE
@ -131,9 +131,9 @@ module ex_stage
// FPU exception - ISSUE_STAGE
output exception_t fpu_exception_o,
// ALU2 instruction is valid - ISSUE_STAGE
input logic [SUPERSCALAR:0] alu2_valid_i,
input logic [CVA6Cfg.NrIssuePorts-1:0] alu2_valid_i,
// CVXIF instruction is valid - ISSUE_STAGE
input logic [SUPERSCALAR:0] x_valid_i,
input logic [CVA6Cfg.NrIssuePorts-1:0] x_valid_i,
// CVXIF is ready - ISSUE_STAGE
output logic x_ready_o,
// undecoded instruction - ISSUE_STAGE
@ -265,7 +265,7 @@ module ex_stage
logic [CVA6Cfg.TRANS_ID_BITS-1:0] mult_trans_id;
logic mult_valid;
logic [SUPERSCALAR:0] one_cycle_select;
logic [CVA6Cfg.NrIssuePorts-1:0] one_cycle_select;
assign one_cycle_select = alu_valid_i | branch_valid_i | csr_valid_i;
fu_data_t one_cycle_data;
@ -273,7 +273,7 @@ module ex_stage
// data silence operation
one_cycle_data = one_cycle_select[0] ? fu_data_i[0] : '0;
if (SUPERSCALAR) begin
if (CVA6Cfg.SuperscalarEn) begin
if (one_cycle_select[1]) begin
one_cycle_data = fu_data_i[1];
end
@ -363,7 +363,7 @@ module ex_stage
// input silencing of multiplier
always_comb begin
mult_data = mult_valid_i[0] ? fu_data_i[0] : '0;
if (SUPERSCALAR) begin
if (CVA6Cfg.SuperscalarEn) begin
if (mult_valid_i[1]) begin
mult_data = fu_data_i[1];
end
@ -399,7 +399,7 @@ module ex_stage
fu_data_t fpu_data;
always_comb begin
fpu_data = fpu_valid_i[0] ? fu_data_i[0] : '0;
if (SUPERSCALAR) begin
if (CVA6Cfg.SuperscalarEn) begin
if (fpu_valid_i[1]) begin
fpu_data = fu_data_i[1];
end
@ -439,7 +439,7 @@ module ex_stage
// ALU2
// ----------------
fu_data_t alu2_data;
if (SUPERSCALAR) begin : alu2_gen
if (CVA6Cfg.SuperscalarEn) begin : alu2_gen
always_comb begin
alu2_data = alu2_valid_i[0] ? fu_data_i[0] : '0;
if (alu2_valid_i[1]) begin
@ -464,7 +464,7 @@ module ex_stage
// result MUX
// This is really explicit so that synthesis tools can elide unused signals
if (SUPERSCALAR) begin
if (CVA6Cfg.SuperscalarEn) begin
if (CVA6Cfg.FpPresent) begin
assign fpu_valid_o = fpu_valid || |alu2_valid_i;
assign fpu_result_o = fpu_valid ? fpu_result : alu2_result;
@ -495,7 +495,7 @@ module ex_stage
lsu_data = lsu_valid_i[0] ? fu_data_i[0] : '0;
lsu_tinst = tinst_i[0];
if (SUPERSCALAR) begin
if (CVA6Cfg.SuperscalarEn) begin
if (lsu_valid_i[1]) begin
lsu_data = fu_data_i[1];
lsu_tinst = tinst_i[1];
@ -582,7 +582,7 @@ module ex_stage
fu_data_t cvxif_data;
always_comb begin
cvxif_data = x_valid_i[0] ? fu_data_i[0] : '0;
if (SUPERSCALAR) begin
if (CVA6Cfg.SuperscalarEn) begin
if (x_valid_i[1]) begin
cvxif_data = fu_data_i[1];
end

6
core/frontend/frontend.sv
View file

@ -59,11 +59,11 @@ module frontend
// Handshake between CACHE and FRONTEND (fetch) - CACHES
input icache_drsp_t icache_dreq_i,
// Handshake's data between fetch and decode - ID_STAGE
output fetch_entry_t [ariane_pkg::SUPERSCALAR:0] fetch_entry_o,
output fetch_entry_t [CVA6Cfg.NrIssuePorts-1:0] fetch_entry_o,
// Handshake's valid between fetch and decode - ID_STAGE
output logic [ariane_pkg::SUPERSCALAR:0] fetch_entry_valid_o,
output logic [CVA6Cfg.NrIssuePorts-1:0] fetch_entry_valid_o,
// Handshake's ready between fetch and decode - ID_STAGE
input logic [ariane_pkg::SUPERSCALAR:0] fetch_entry_ready_i
input logic [CVA6Cfg.NrIssuePorts-1:0] fetch_entry_ready_i
);
localparam type bht_update_t = struct packed {

30
core/frontend/instr_queue.sv
View file

@ -81,15 +81,15 @@ module instr_queue
// Address at which to replay the fetch - FRONTEND
output logic [CVA6Cfg.VLEN-1:0] replay_addr_o,
// Handshake’s data with ID_STAGE - ID_STAGE
output fetch_entry_t [ariane_pkg::SUPERSCALAR:0] fetch_entry_o,
output fetch_entry_t [CVA6Cfg.NrIssuePorts-1:0] fetch_entry_o,
// Handshake’s valid with ID_STAGE - ID_STAGE
output logic [ariane_pkg::SUPERSCALAR:0] fetch_entry_valid_o,
output logic [CVA6Cfg.NrIssuePorts-1:0] fetch_entry_valid_o,
// Handshake’s ready with ID_STAGE - ID_STAGE
input logic [ariane_pkg::SUPERSCALAR:0] fetch_entry_ready_i
input logic [CVA6Cfg.NrIssuePorts-1:0] fetch_entry_ready_i
);
// Calculate next index based on whether superscalar is enabled or not.
localparam NID = ariane_pkg::SUPERSCALAR > 0 ? 1 : 0;
localparam NID = CVA6Cfg.SuperscalarEn ? 1 : 0;
typedef struct packed {
logic [31:0] instr; // instruction word
@ -127,13 +127,13 @@ ariane_pkg::FETCH_FIFO_DEPTH
// output FIFO select, one-hot
logic [CVA6Cfg.INSTR_PER_FETCH-1:0] idx_ds_d, idx_ds_q;
// rotated by N
logic [ariane_pkg::SUPERSCALAR+1:0][CVA6Cfg.INSTR_PER_FETCH-1:0] idx_ds;
logic [CVA6Cfg.NrIssuePorts:0][CVA6Cfg.INSTR_PER_FETCH-1:0] idx_ds;
logic [CVA6Cfg.VLEN-1:0] pc_d, pc_q; // current PC
logic [ariane_pkg::SUPERSCALAR+1:0][CVA6Cfg.VLEN-1:0] pc_j;
logic [CVA6Cfg.NrIssuePorts:0][CVA6Cfg.VLEN-1:0] pc_j;
logic reset_address_d, reset_address_q; // we need to re-set the address because of a flush
logic [ariane_pkg::SUPERSCALAR:0] fetch_entry_is_cf, fetch_entry_fire;
logic [CVA6Cfg.NrIssuePorts-1:0] fetch_entry_is_cf, fetch_entry_fire;
logic [CVA6Cfg.INSTR_PER_FETCH*2-2:0] branch_mask_extended;
logic [CVA6Cfg.INSTR_PER_FETCH-1:0] branch_mask;
@ -305,13 +305,13 @@ ariane_pkg::FETCH_FIFO_DEPTH
// ----------------------
// as long as there is at least one queue which can take the value we have a valid instruction
assign fetch_entry_valid_o[0] = ~(&instr_queue_empty);
if (ariane_pkg::SUPERSCALAR > 0) begin : gen_fetch_entry_valid_1
if (CVA6Cfg.SuperscalarEn) begin : gen_fetch_entry_valid_1
// TODO Maybe this additional fetch_entry_is_cf check is useless as issue-stage already performs it?
assign fetch_entry_valid_o[NID] = ~|(instr_queue_empty & idx_ds[1]) & ~(&fetch_entry_is_cf);
end
assign idx_ds[0] = idx_ds_q;
for (genvar i = 0; i <= ariane_pkg::SUPERSCALAR; i++) begin
for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
if (CVA6Cfg.INSTR_PER_FETCH > 1) begin
assign idx_ds[i+1] = {
idx_ds[i][CVA6Cfg.INSTR_PER_FETCH-2:0], idx_ds[i][CVA6Cfg.INSTR_PER_FETCH-1]
@ -327,7 +327,7 @@ ariane_pkg::FETCH_FIFO_DEPTH
pop_instr = '0;
// assemble fetch entry
for (int unsigned i = 0; i <= ariane_pkg::SUPERSCALAR; i++) begin
for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
fetch_entry_o[i].instruction = '0;
fetch_entry_o[i].address = pc_j[i];
fetch_entry_o[i].ex.valid = 1'b0;
@ -367,7 +367,7 @@ ariane_pkg::FETCH_FIFO_DEPTH
pop_instr[i] = fetch_entry_fire[0];
end
if (ariane_pkg::SUPERSCALAR > 0) begin
if (CVA6Cfg.SuperscalarEn) begin
if (idx_ds[1][i]) begin
if (instr_data_out[i].ex == ariane_pkg::FE_INSTR_ACCESS_FAULT) begin
fetch_entry_o[NID].ex.cause = riscv::INSTR_ACCESS_FAULT;
@ -385,7 +385,7 @@ ariane_pkg::FETCH_FIFO_DEPTH
end
// rotate the pointer left
if (fetch_entry_fire[0]) begin
if (ariane_pkg::SUPERSCALAR > 0) begin
if (CVA6Cfg.SuperscalarEn) begin
idx_ds_d = fetch_entry_fire[NID] ? idx_ds[2] : idx_ds[1];
end else begin
idx_ds_d = idx_ds[1];
@ -425,7 +425,7 @@ ariane_pkg::FETCH_FIFO_DEPTH
end
end
for (genvar i = 0; i <= ariane_pkg::SUPERSCALAR; i++) begin
for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
assign fetch_entry_is_cf[i] = fetch_entry_o[i].branch_predict.cf != ariane_pkg::NoCF;
assign fetch_entry_fire[i] = fetch_entry_valid_o[i] & fetch_entry_ready_i[i];
end
@ -436,7 +436,7 @@ ariane_pkg::FETCH_FIFO_DEPTH
// Calculate (Next) PC
// ----------------------
assign pc_j[0] = pc_q;
for (genvar i = 0; i <= ariane_pkg::SUPERSCALAR; i++) begin
for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
assign pc_j[i+1] = fetch_entry_is_cf[i] ? address_out : (
pc_j[i] + ((fetch_entry_o[i].instruction[1:0] != 2'b11) ? 'd2 : 'd4)
);
@ -448,7 +448,7 @@ ariane_pkg::FETCH_FIFO_DEPTH
if (fetch_entry_fire[0]) begin
pc_d = pc_j[1];
if (ariane_pkg::SUPERSCALAR > 0) begin
if (CVA6Cfg.SuperscalarEn) begin
if (fetch_entry_fire[NID]) begin
pc_d = pc_j[2];
end

64
core/id_stage.sv
View file

@ -32,23 +32,23 @@ module id_stage #(
// Debug (async) request - SUBSYSTEM
input logic debug_req_i,
// Handshake's data between fetch and decode - FRONTEND
input fetch_entry_t [ariane_pkg::SUPERSCALAR:0] fetch_entry_i,
input fetch_entry_t [CVA6Cfg.NrIssuePorts-1:0] fetch_entry_i,
// Handshake's valid between fetch and decode - FRONTEND
input logic [ariane_pkg::SUPERSCALAR:0] fetch_entry_valid_i,
input logic [CVA6Cfg.NrIssuePorts-1:0] fetch_entry_valid_i,
// Handshake's ready between fetch and decode - FRONTEND
output logic [ariane_pkg::SUPERSCALAR:0] fetch_entry_ready_o,
output logic [CVA6Cfg.NrIssuePorts-1:0] fetch_entry_ready_o,
// Handshake's data between decode and issue - ISSUE
output scoreboard_entry_t [ariane_pkg::SUPERSCALAR:0] issue_entry_o,
output scoreboard_entry_t [CVA6Cfg.NrIssuePorts-1:0] issue_entry_o,
// Instruction value - ISSUE
output logic [ariane_pkg::SUPERSCALAR:0][31:0] orig_instr_o,
output logic [CVA6Cfg.NrIssuePorts-1:0][31:0] orig_instr_o,
// Handshake's valid between decode and issue - ISSUE
output logic [ariane_pkg::SUPERSCALAR:0] issue_entry_valid_o,
output logic [CVA6Cfg.NrIssuePorts-1:0] issue_entry_valid_o,
// Report if instruction is a control flow instruction - ISSUE
output logic [ariane_pkg::SUPERSCALAR:0] is_ctrl_flow_o,
output logic [CVA6Cfg.NrIssuePorts-1:0] is_ctrl_flow_o,
// Handshake's acknowlege between decode and issue - ISSUE
input logic [ariane_pkg::SUPERSCALAR:0] issue_instr_ack_i,
input logic [CVA6Cfg.NrIssuePorts-1:0] issue_instr_ack_i,
// Information dedicated to RVFI - RVFI
output logic [ariane_pkg::SUPERSCALAR:0] rvfi_is_compressed_o,
output logic [CVA6Cfg.NrIssuePorts-1:0] rvfi_is_compressed_o,
// Current privilege level - CSR_REGFILE
input riscv::priv_lvl_t priv_lvl_i,
// Current virtualization mode - CSR_REGFILE
@ -85,28 +85,28 @@ module id_stage #(
logic [31:0] orig_instr;
logic is_ctrl_flow;
} issue_struct_t;
issue_struct_t [ariane_pkg::SUPERSCALAR:0] issue_n, issue_q;
issue_struct_t [CVA6Cfg.NrIssuePorts-1:0] issue_n, issue_q;
logic [ariane_pkg::SUPERSCALAR:0] is_control_flow_instr;
scoreboard_entry_t [ariane_pkg::SUPERSCALAR:0] decoded_instruction;
logic [ariane_pkg::SUPERSCALAR:0][31:0] orig_instr;
logic [CVA6Cfg.NrIssuePorts-1:0] is_control_flow_instr;
scoreboard_entry_t [CVA6Cfg.NrIssuePorts-1:0] decoded_instruction;
logic [CVA6Cfg.NrIssuePorts-1:0][31:0] orig_instr;
logic [ariane_pkg::SUPERSCALAR:0] is_illegal;
logic [ariane_pkg::SUPERSCALAR:0] is_illegal_cmp;
logic [ariane_pkg::SUPERSCALAR:0][31:0] instruction;
logic [ariane_pkg::SUPERSCALAR:0][31:0] compressed_instr;
logic [ariane_pkg::SUPERSCALAR:0] is_compressed;
logic [ariane_pkg::SUPERSCALAR:0] is_compressed_cmp;
logic [ariane_pkg::SUPERSCALAR:0] is_macro_instr_i;
logic stall_instr_fetch;
logic is_last_macro_instr_o;
logic is_double_rd_macro_instr_o;
logic [CVA6Cfg.NrIssuePorts-1:0] is_illegal;
logic [CVA6Cfg.NrIssuePorts-1:0] is_illegal_cmp;
logic [CVA6Cfg.NrIssuePorts-1:0][31:0] instruction;
logic [CVA6Cfg.NrIssuePorts-1:0][31:0] compressed_instr;
logic [CVA6Cfg.NrIssuePorts-1:0] is_compressed;
logic [CVA6Cfg.NrIssuePorts-1:0] is_compressed_cmp;
logic [CVA6Cfg.NrIssuePorts-1:0] is_macro_instr_i;
logic stall_instr_fetch;
logic is_last_macro_instr_o;
logic is_double_rd_macro_instr_o;
if (CVA6Cfg.RVC) begin
// ---------------------------------------------------------
// 1. Check if they are compressed and expand in case they are
// ---------------------------------------------------------
for (genvar i = 0; i <= ariane_pkg::SUPERSCALAR; i++) begin
for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
compressed_decoder #(
.CVA6Cfg(CVA6Cfg)
) compressed_decoder_i (
@ -136,10 +136,10 @@ module id_stage #(
.is_last_macro_instr_o (is_last_macro_instr_o),
.is_double_rd_macro_instr_o(is_double_rd_macro_instr_o)
);
if (ariane_pkg::SUPERSCALAR > 0) begin
assign instruction[ariane_pkg::SUPERSCALAR] = '0;
assign is_illegal_cmp[ariane_pkg::SUPERSCALAR] = '0;
assign is_compressed_cmp[ariane_pkg::SUPERSCALAR] = '0;
if (CVA6Cfg.SuperscalarEn) begin
assign instruction[CVA6Cfg.NrIssuePorts-1] = '0;
assign is_illegal_cmp[CVA6Cfg.NrIssuePorts-1] = '0;
assign is_compressed_cmp[CVA6Cfg.NrIssuePorts-1] = '0;
end
end else begin
assign instruction = compressed_instr;
@ -149,7 +149,7 @@ module id_stage #(
assign is_double_rd_macro_instr_o = '0;
end
end else begin
for (genvar i = 0; i <= ariane_pkg::SUPERSCALAR; i++) begin
for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
assign instruction[i] = fetch_entry_i[i].instruction;
end
assign is_illegal_cmp = '0;
@ -163,7 +163,7 @@ module id_stage #(
// ---------------------------------------------------------
// 2. Decode and emit instruction to issue stage
// ---------------------------------------------------------
for (genvar i = 0; i <= ariane_pkg::SUPERSCALAR; i++) begin
for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
decoder #(
.CVA6Cfg(CVA6Cfg),
.branchpredict_sbe_t(branchpredict_sbe_t),
@ -207,14 +207,14 @@ module id_stage #(
// ------------------
// Pipeline Register
// ------------------
for (genvar i = 0; i <= ariane_pkg::SUPERSCALAR; i++) begin
for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
assign issue_entry_o[i] = issue_q[i].sbe;
assign issue_entry_valid_o[i] = issue_q[i].valid;
assign is_ctrl_flow_o[i] = issue_q[i].is_ctrl_flow;
assign orig_instr_o[i] = issue_q[i].orig_instr;
end
if (ariane_pkg::SUPERSCALAR) begin
if (CVA6Cfg.SuperscalarEn) begin
always_comb begin
issue_n = issue_q;
fetch_entry_ready_o = '0;

3
core/include/ariane_pkg.sv
View file

@ -168,9 +168,6 @@ package ariane_pkg;
// leave as is (fails with >8 entries and wider fetch width)
localparam int unsigned FETCH_FIFO_DEPTH = 4;
localparam int unsigned SUPERSCALAR = cva6_config_pkg::CVA6ConfigSuperscalarEn;
localparam int unsigned SPECULATIVE_SB = SUPERSCALAR;
typedef enum logic [2:0] {
NoCF, // No control flow prediction
Branch, // Branch

11
core/include/build_config_pkg.sv
View file

@ -43,7 +43,12 @@ package build_config_pkg;
cfg.FpgaEn = CVA6Cfg.FpgaEn;
cfg.TechnoCut = CVA6Cfg.TechnoCut;
cfg.NrCommitPorts = CVA6Cfg.NrCommitPorts;
cfg.SuperscalarEn = CVA6Cfg.SuperscalarEn;
cfg.NrCommitPorts = CVA6Cfg.SuperscalarEn ? unsigned'(2) : CVA6Cfg.NrCommitPorts;
cfg.NrIssuePorts = unsigned'(CVA6Cfg.SuperscalarEn ? 2 : 1);
cfg.SpeculativeSb = CVA6Cfg.SuperscalarEn;
cfg.NrLoadPipeRegs = CVA6Cfg.NrLoadPipeRegs;
cfg.NrStorePipeRegs = CVA6Cfg.NrStorePipeRegs;
cfg.AxiAddrWidth = CVA6Cfg.AxiAddrWidth;
@ -79,7 +84,7 @@ package build_config_pkg;
cfg.XF16Vec = bit'(XF16Vec);
cfg.XF16ALTVec = bit'(XF16ALTVec);
cfg.XF8Vec = bit'(XF8Vec);
cfg.NrRgprPorts = unsigned'(2 << ariane_pkg::SUPERSCALAR);
cfg.NrRgprPorts = unsigned'(CVA6Cfg.SuperscalarEn ? 4 : 2);
cfg.NrWbPorts = unsigned'(NrWbPorts);
cfg.EnableAccelerator = bit'(EnableAccelerator);
cfg.PerfCounterEn = CVA6Cfg.PerfCounterEn;
@ -140,7 +145,7 @@ package build_config_pkg;
cfg.FETCH_USER_EN = CVA6Cfg.FetchUserEn;
cfg.AXI_USER_EN = CVA6Cfg.DataUserEn | CVA6Cfg.FetchUserEn;
cfg.FETCH_WIDTH = 32 << ariane_pkg::SUPERSCALAR;
cfg.FETCH_WIDTH = unsigned'(CVA6Cfg.SuperscalarEn ? 64 : 32);
cfg.FETCH_ALIGN_BITS = $clog2(cfg.FETCH_WIDTH / 8);
cfg.INSTR_PER_FETCH = cfg.FETCH_WIDTH / (CVA6Cfg.RVC ? 16 : 32);
cfg.LOG2_INSTR_PER_FETCH = cfg.INSTR_PER_FETCH > 1 ? $clog2(cfg.INSTR_PER_FETCH) : 1;

17
core/include/config_pkg.sv
View file

@ -170,7 +170,9 @@ package config_pkg;
bit FpgaEn;
// Is Techno Cut instanciated
bit TechnoCut;
// Number of commit ports
// Enable superscalar with 2 issue ports and 2 commit ports
bit SuperscalarEn;
// Number of commit ports. Forced to 2 if SuperscalarEn.
int unsigned NrCommitPorts;
// Load cycle latency number
int unsigned NrLoadPipeRegs;
@ -209,13 +211,14 @@ package config_pkg;
int unsigned ASID_WIDTH;
int unsigned VMID_WIDTH;
bit FpgaEn;
bit TechnoCut;
/// Number of commit ports, i.e., maximum number of instructions that the
/// core can retire per cycle. It can be beneficial to have more commit
/// ports than issue ports, for the scoreboard to empty out in case one
/// instruction stalls a little longer.
bit FpgaEn;
bit TechnoCut;
bit SuperscalarEn;
int unsigned NrCommitPorts;
int unsigned NrIssuePorts;
bit SpeculativeSb;
int unsigned NrLoadPipeRegs;
int unsigned NrStorePipeRegs;
/// AXI parameters.

3
core/include/cv32a65x_config_pkg.sv
View file

@ -18,14 +18,13 @@ package cva6_config_pkg;
localparam CVA6ConfigAxiDataWidth = 64; // axi_pkg.sv
localparam CVA6ConfigDataUserWidth = 32; // axi_pkg.sv
localparam CVA6ConfigSuperscalarEn = 0; // superscalar
localparam CVA6ConfigNrScoreboardEntries = 4; // cvxif_pkg.sv
localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
XLEN: unsigned'(CVA6ConfigXlen),
FpgaEn: bit'(0),
TechnoCut: bit'(1),
SuperscalarEn: bit'(0),
NrCommitPorts: unsigned'(1),
AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),

5
core/include/cv32a6_ima_sv32_fpga_config_pkg.sv
View file

@ -48,8 +48,6 @@ package cva6_config_pkg;
localparam CVA6ConfigWtDcacheWbufDepth = 2;
localparam CVA6ConfigSuperscalarEn = 0;
localparam CVA6ConfigNrCommitPorts = 1;
localparam CVA6ConfigNrScoreboardEntries = 4;
localparam CVA6ConfigFpgaEn = 1;
@ -78,7 +76,8 @@ package cva6_config_pkg;
XLEN: unsigned'(CVA6ConfigXlen),
FpgaEn: bit'(CVA6ConfigFpgaEn),
TechnoCut: bit'(0),
NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts),
SuperscalarEn: bit'(0),
NrCommitPorts: unsigned'(1),
AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),
AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth),

5
core/include/cv32a6_imac_sv0_config_pkg.sv
View file

@ -48,8 +48,6 @@ package cva6_config_pkg;
localparam CVA6ConfigWtDcacheWbufDepth = 8;
localparam CVA6ConfigSuperscalarEn = 0;
localparam CVA6ConfigNrCommitPorts = 2;
localparam CVA6ConfigNrScoreboardEntries = 8;
localparam CVA6ConfigNrLoadBufEntries = 2;
@ -78,7 +76,8 @@ package cva6_config_pkg;
XLEN: unsigned'(CVA6ConfigXlen),
FpgaEn: bit'(CVA6ConfigFpgaEn),
TechnoCut: bit'(0),
NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts),
SuperscalarEn: bit'(0),
NrCommitPorts: unsigned'(2),
AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),
AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth),

5
core/include/cv32a6_imac_sv32_config_pkg.sv
View file

@ -48,8 +48,6 @@ package cva6_config_pkg;
localparam CVA6ConfigWtDcacheWbufDepth = 8;
localparam CVA6ConfigSuperscalarEn = 0;
localparam CVA6ConfigNrCommitPorts = 2;
localparam CVA6ConfigNrScoreboardEntries = 8;
localparam CVA6ConfigFpgaEn = 0;
@ -78,7 +76,8 @@ package cva6_config_pkg;
XLEN: unsigned'(CVA6ConfigXlen),
FpgaEn: bit'(CVA6ConfigFpgaEn),
TechnoCut: bit'(0),
NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts),
SuperscalarEn: bit'(0),
NrCommitPorts: unsigned'(2),
AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),
AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth),

5
core/include/cv32a6_imafc_sv32_config_pkg.sv
View file

@ -48,8 +48,6 @@ package cva6_config_pkg;
localparam CVA6ConfigWtDcacheWbufDepth = 8;
localparam CVA6ConfigSuperscalarEn = 0;
localparam CVA6ConfigNrCommitPorts = 2;
localparam CVA6ConfigNrScoreboardEntries = 8;
localparam CVA6ConfigFpgaEn = 0;
@ -78,7 +76,8 @@ package cva6_config_pkg;
XLEN: unsigned'(CVA6ConfigXlen),
FpgaEn: bit'(CVA6ConfigFpgaEn),
TechnoCut: bit'(0),
NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts),
SuperscalarEn: bit'(0),
NrCommitPorts: unsigned'(2),
AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),
AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth),

5
core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv
View file

@ -48,8 +48,6 @@ package cva6_config_pkg;
localparam CVA6ConfigWtDcacheWbufDepth = 8;
localparam CVA6ConfigSuperscalarEn = 0;
localparam CVA6ConfigNrCommitPorts = 2;
localparam CVA6ConfigNrScoreboardEntries = 8;
localparam CVA6ConfigFpgaEn = 0;
@ -78,7 +76,8 @@ package cva6_config_pkg;
XLEN: unsigned'(CVA6ConfigXlen),
FpgaEn: bit'(CVA6ConfigFpgaEn),
TechnoCut: bit'(0),
NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts),
SuperscalarEn: bit'(0),
NrCommitPorts: unsigned'(2),
AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),
AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth),

5
core/include/cv64a6_imafdc_sv39_config_pkg.sv
View file

@ -48,8 +48,6 @@ package cva6_config_pkg;
localparam CVA6ConfigWtDcacheWbufDepth = 8;
localparam CVA6ConfigSuperscalarEn = 0;
localparam CVA6ConfigNrCommitPorts = 2;
localparam CVA6ConfigNrScoreboardEntries = 8;
localparam CVA6ConfigFpgaEn = 0;
@ -78,7 +76,8 @@ package cva6_config_pkg;
XLEN: unsigned'(CVA6ConfigXlen),
FpgaEn: bit'(CVA6ConfigFpgaEn),
TechnoCut: bit'(0),
NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts),
SuperscalarEn: bit'(0),
NrCommitPorts: unsigned'(2),
AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),
AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth),

5
core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv
View file

@ -55,8 +55,6 @@ package cva6_config_pkg;
localparam CVA6ConfigWtDcacheWbufDepth = 8;
localparam CVA6ConfigSuperscalarEn = 0;
localparam CVA6ConfigNrCommitPorts = 2;
localparam CVA6ConfigNrScoreboardEntries = 8;
localparam CVA6ConfigFpgaEn = 0;
@ -85,7 +83,8 @@ package cva6_config_pkg;
XLEN: unsigned'(CVA6ConfigXlen),
FpgaEn: bit'(CVA6ConfigFpgaEn),
TechnoCut: bit'(0),
NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts),
SuperscalarEn: bit'(0),
NrCommitPorts: unsigned'(2),
AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),
AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth),

5
core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv
View file

@ -48,8 +48,6 @@ package cva6_config_pkg;
localparam CVA6ConfigWtDcacheWbufDepth = 8;
localparam CVA6ConfigSuperscalarEn = 0;
localparam CVA6ConfigNrCommitPorts = 2;
localparam CVA6ConfigNrScoreboardEntries = 8;
localparam CVA6ConfigFpgaEn = 0;
@ -78,7 +76,8 @@ package cva6_config_pkg;
XLEN: unsigned'(CVA6ConfigXlen),
FpgaEn: bit'(CVA6ConfigFpgaEn),
TechnoCut: bit'(0),
NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts),
SuperscalarEn: bit'(0),
NrCommitPorts: unsigned'(2),
AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),
AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth),

5
core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv
View file

@ -48,8 +48,6 @@ package cva6_config_pkg;
localparam CVA6ConfigWtDcacheWbufDepth = 8;
localparam CVA6ConfigSuperscalarEn = 0;
localparam CVA6ConfigNrCommitPorts = 2;
localparam CVA6ConfigNrScoreboardEntries = 8;
localparam CVA6ConfigFpgaEn = 0;
@ -78,7 +76,8 @@ package cva6_config_pkg;
XLEN: unsigned'(CVA6ConfigXlen),
FpgaEn: bit'(CVA6ConfigFpgaEn),
TechnoCut: bit'(0),
NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts),
SuperscalarEn: bit'(0),
NrCommitPorts: unsigned'(2),
AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),
AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth),

5
core/include/cv64a6_imafdch_sv39_config_pkg.sv
View file

@ -48,8 +48,6 @@ package cva6_config_pkg;
localparam CVA6ConfigWtDcacheWbufDepth = 8;
localparam CVA6ConfigSuperscalarEn = 0;
localparam CVA6ConfigNrCommitPorts = 2;
localparam CVA6ConfigNrScoreboardEntries = 8;
localparam CVA6ConfigFpgaEn = 0;
@ -78,7 +76,8 @@ package cva6_config_pkg;
XLEN: unsigned'(CVA6ConfigXlen),
FpgaEn: bit'(CVA6ConfigFpgaEn),
TechnoCut: bit'(0),
NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts),
SuperscalarEn: bit'(0),
NrCommitPorts: unsigned'(2),
AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),
AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth),

5
core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv
View file

@ -48,8 +48,6 @@ package cva6_config_pkg;
localparam CVA6ConfigWtDcacheWbufDepth = 8;
localparam CVA6ConfigSuperscalarEn = 0;
localparam CVA6ConfigNrCommitPorts = 2;
localparam CVA6ConfigNrScoreboardEntries = 8;
localparam CVA6ConfigFpgaEn = 0;
@ -78,7 +76,8 @@ package cva6_config_pkg;
XLEN: unsigned'(CVA6ConfigXlen),
FpgaEn: bit'(CVA6ConfigFpgaEn),
TechnoCut: bit'(CVA6ConfigTechnoCut),
NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts),
SuperscalarEn: bit'(0),
NrCommitPorts: unsigned'(2),
AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),
AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth),

5
core/include/cv64a6_imafdcv_sv39_config_pkg.sv
View file

@ -48,8 +48,6 @@ package cva6_config_pkg;
localparam CVA6ConfigWtDcacheWbufDepth = 8;
localparam CVA6ConfigSuperscalarEn = 0;
localparam CVA6ConfigNrCommitPorts = 1;
localparam CVA6ConfigNrScoreboardEntries = 8;
localparam CVA6ConfigFpgaEn = 0;
@ -78,7 +76,8 @@ package cva6_config_pkg;
XLEN: unsigned'(CVA6ConfigXlen),
FpgaEn: bit'(CVA6ConfigFpgaEn),
TechnoCut: bit'(0),
NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts),
SuperscalarEn: bit'(0),
NrCommitPorts: unsigned'(1),
AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),
AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth),

4
core/include/cv64a6_mmu_config_pkg.sv
View file

@ -12,7 +12,6 @@ package cva6_config_pkg;
localparam CVA6ConfigXlen = 64;
localparam CVA6ConfigBExtEn = 1; // UVM
localparam CVA6ConfigNrCommitPorts = 1; // UVM
localparam CVA6ConfigRvfiTrace = 1;
localparam CVA6ConfigAxiIdWidth = 4; // axi_pkg.sv
@ -30,7 +29,8 @@ package cva6_config_pkg;
XLEN: unsigned'(CVA6ConfigXlen),
FpgaEn: bit'(0),
TechnoCut: bit'(0),
NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts),
SuperscalarEn: bit'(0),
NrCommitPorts: unsigned'(1),
AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),
AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),
AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth),

18
core/include/rvfi_types.svh
View file

@ -93,18 +93,18 @@
// RVFI PROBES
`define RVFI_PROBES_INSTR_T(Cfg) struct packed { \
logic [ariane_pkg::SUPERSCALAR:0][Cfg.TRANS_ID_BITS-1:0] issue_pointer; \
logic [Cfg.NrIssuePorts-1:0][Cfg.TRANS_ID_BITS-1:0] issue_pointer; \
logic [Cfg.NrCommitPorts-1:0][Cfg.TRANS_ID_BITS-1:0] commit_pointer; \
logic flush_unissued_instr; \
logic [ariane_pkg::SUPERSCALAR:0] decoded_instr_valid; \
logic [ariane_pkg::SUPERSCALAR:0] decoded_instr_ack; \
logic [Cfg.NrIssuePorts-1:0] decoded_instr_valid; \
logic [Cfg.NrIssuePorts-1:0] decoded_instr_ack; \
logic flush; \
logic [ariane_pkg::SUPERSCALAR:0] issue_instr_ack; \
logic [ariane_pkg::SUPERSCALAR:0] fetch_entry_valid; \
logic [ariane_pkg::SUPERSCALAR:0][31:0] instruction; \
logic [ariane_pkg::SUPERSCALAR:0] is_compressed; \
logic [ariane_pkg::SUPERSCALAR:0][Cfg.VLEN-1:0] rs1_forwarding; \
logic [ariane_pkg::SUPERSCALAR:0][Cfg.VLEN-1:0] rs2_forwarding; \
logic [Cfg.NrIssuePorts-1:0] issue_instr_ack; \
logic [Cfg.NrIssuePorts-1:0] fetch_entry_valid; \
logic [Cfg.NrIssuePorts-1:0][31:0] instruction; \
logic [Cfg.NrIssuePorts-1:0] is_compressed; \
logic [Cfg.NrIssuePorts-1:0][Cfg.VLEN-1:0] rs1_forwarding; \
logic [Cfg.NrIssuePorts-1:0][Cfg.VLEN-1:0] rs2_forwarding; \
logic [Cfg.NrCommitPorts-1:0][Cfg.VLEN-1:0] commit_instr_pc; \
ariane_pkg::fu_op [Cfg.NrCommitPorts-1:0] commit_instr_op; \
logic [Cfg.NrCommitPorts-1:0][ariane_pkg::REG_ADDR_SIZE-1:0] commit_instr_rs1; \

136
core/issue_read_operands.sv
View file

@ -32,42 +32,42 @@ module issue_read_operands
// Stall inserted by Acc dispatcher - ACC_DISPATCHER
input logic stall_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input scoreboard_entry_t [SUPERSCALAR:0] issue_instr_i,
input scoreboard_entry_t [CVA6Cfg.NrIssuePorts-1:0] issue_instr_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic [SUPERSCALAR:0][31:0] orig_instr_i,
input logic [CVA6Cfg.NrIssuePorts-1:0][31:0] orig_instr_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic [SUPERSCALAR:0] issue_instr_valid_i,
input logic [CVA6Cfg.NrIssuePorts-1:0] issue_instr_valid_i,
// Issue stage acknowledge - TO_BE_COMPLETED
output logic [SUPERSCALAR:0] issue_ack_o,
output logic [CVA6Cfg.NrIssuePorts-1:0] issue_ack_o,
// rs1 operand address - scoreboard
output logic [SUPERSCALAR:0][REG_ADDR_SIZE-1:0] rs1_o,
output logic [CVA6Cfg.NrIssuePorts-1:0][REG_ADDR_SIZE-1:0] rs1_o,
// rs1 operand - scoreboard
input logic [SUPERSCALAR:0][CVA6Cfg.XLEN-1:0] rs1_i,
input logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rs1_i,
// rs1 operand is valid - scoreboard
input logic [SUPERSCALAR:0] rs1_valid_i,
input logic [CVA6Cfg.NrIssuePorts-1:0] rs1_valid_i,
// rs2 operand address - scoreboard
output logic [SUPERSCALAR:0][REG_ADDR_SIZE-1:0] rs2_o,
output logic [CVA6Cfg.NrIssuePorts-1:0][REG_ADDR_SIZE-1:0] rs2_o,
// rs2 operand - scoreboard
input logic [SUPERSCALAR:0][CVA6Cfg.XLEN-1:0] rs2_i,
input logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rs2_i,
// rs2 operand is valid - scoreboard
input logic [SUPERSCALAR:0] rs2_valid_i,
input logic [CVA6Cfg.NrIssuePorts-1:0] rs2_valid_i,
// rs3 operand address - scoreboard
output logic [SUPERSCALAR:0][REG_ADDR_SIZE-1:0] rs3_o,
output logic [CVA6Cfg.NrIssuePorts-1:0][REG_ADDR_SIZE-1:0] rs3_o,
// rs3 operand - scoreboard
input rs3_len_t [SUPERSCALAR:0] rs3_i,
input rs3_len_t [CVA6Cfg.NrIssuePorts-1:0] rs3_i,
// rs3 operand is valid - scoreboard
input logic [SUPERSCALAR:0] rs3_valid_i,
input logic [CVA6Cfg.NrIssuePorts-1:0] rs3_valid_i,
// get clobber input
// TO_BE_COMPLETED - TO_BE_COMPLETED
input fu_t [2**REG_ADDR_SIZE-1:0] rd_clobber_gpr_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input fu_t [2**REG_ADDR_SIZE-1:0] rd_clobber_fpr_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
output fu_data_t [SUPERSCALAR:0] fu_data_o,
output fu_data_t [CVA6Cfg.NrIssuePorts-1:0] fu_data_o,
// Unregistered version of fu_data_o.operanda - TO_BE_COMPLETED
output logic [SUPERSCALAR:0][CVA6Cfg.XLEN-1:0] rs1_forwarding_o,
output logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rs1_forwarding_o,
// Unregistered version of fu_data_o.operandb - TO_BE_COMPLETED
output logic [SUPERSCALAR:0][CVA6Cfg.XLEN-1:0] rs2_forwarding_o,
output logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rs2_forwarding_o,
// Instruction pc - TO_BE_COMPLETED
output logic [CVA6Cfg.VLEN-1:0] pc_o,
// Is compressed instruction - TO_BE_COMPLETED
@ -75,33 +75,33 @@ module issue_read_operands
// Fixed Latency Unit ready to accept new request - TO_BE_COMPLETED
input logic flu_ready_i,
// ALU output is valid - TO_BE_COMPLETED
output logic [SUPERSCALAR:0] alu_valid_o,
output logic [CVA6Cfg.NrIssuePorts-1:0] alu_valid_o,
// Branch instruction is valid - TO_BE_COMPLETED
output logic [SUPERSCALAR:0] branch_valid_o,
output logic [CVA6Cfg.NrIssuePorts-1:0] branch_valid_o,
// Transformed instruction - TO_BE_COMPLETED
output logic [SUPERSCALAR:0][31:0] tinst_o,
output logic [CVA6Cfg.NrIssuePorts-1:0][31:0] tinst_o,
// TO_BE_COMPLETED - TO_BE_COMPLETED
output branchpredict_sbe_t branch_predict_o,
// Load Store Unit is ready - TO_BE_COMPLETED
input logic lsu_ready_i,
// Load Store Unit result is valid - TO_BE_COMPLETED
output logic [SUPERSCALAR:0] lsu_valid_o,
output logic [CVA6Cfg.NrIssuePorts-1:0] lsu_valid_o,
// Mult result is valid - TO_BE_COMPLETED
output logic [SUPERSCALAR:0] mult_valid_o,
output logic [CVA6Cfg.NrIssuePorts-1:0] mult_valid_o,
// FPU is ready - TO_BE_COMPLETED
input logic fpu_ready_i,
// FPU result is valid - TO_BE_COMPLETED
output logic [SUPERSCALAR:0] fpu_valid_o,
output logic [CVA6Cfg.NrIssuePorts-1:0] fpu_valid_o,
// FPU fmt field from instruction - TO_BE_COMPLETED
output logic [1:0] fpu_fmt_o,
// FPU rm field from isntruction - TO_BE_COMPLETED
output logic [2:0] fpu_rm_o,
// ALU output is valid - TO_BE_COMPLETED
output logic [SUPERSCALAR:0] alu2_valid_o,
output logic [CVA6Cfg.NrIssuePorts-1:0] alu2_valid_o,
// CSR result is valid - TO_BE_COMPLETED
output logic [SUPERSCALAR:0] csr_valid_o,
output logic [CVA6Cfg.NrIssuePorts-1:0] csr_valid_o,
// CVXIF result is valid - TO_BE_COMPLETED
output logic [SUPERSCALAR:0] cvxif_valid_o,
output logic [CVA6Cfg.NrIssuePorts-1:0] cvxif_valid_o,
// CVXIF is ready - TO_BE_COMPLETED
input logic cvxif_ready_i,
// CVXIF offloaded instruction - TO_BE_COMPLETED
@ -119,40 +119,40 @@ module issue_read_operands
output logic stall_issue_o
);
localparam OPERANDS_PER_INSTR = CVA6Cfg.NrRgprPorts >> SUPERSCALAR;
localparam OPERANDS_PER_INSTR = CVA6Cfg.NrRgprPorts / CVA6Cfg.NrIssuePorts;
typedef struct packed {
logic none, load, store, alu, alu2, ctrl_flow, mult, csr, fpu, fpu_vec, cvxif, accel;
} fus_busy_t;
logic [SUPERSCALAR:0] stall;
logic [SUPERSCALAR:0] fu_busy; // functional unit is busy
fus_busy_t [SUPERSCALAR:0] fus_busy; // which functional units are considered busy
logic [CVA6Cfg.NrIssuePorts-1:0] stall;
logic [CVA6Cfg.NrIssuePorts-1:0] fu_busy; // functional unit is busy
fus_busy_t [CVA6Cfg.NrIssuePorts-1:0] fus_busy; // which functional units are considered busy
// operands coming from regfile
logic [SUPERSCALAR:0][CVA6Cfg.XLEN-1:0] operand_a_regfile, operand_b_regfile;
logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] operand_a_regfile, operand_b_regfile;
// third operand from fp regfile or gp regfile if NR_RGPR_PORTS == 3
rs3_len_t [SUPERSCALAR:0] operand_c_regfile, operand_c_gpr;
rs3_len_t [CVA6Cfg.NrIssuePorts-1:0] operand_c_regfile, operand_c_gpr;
rs3_len_t operand_c_fpr;
// output flipflop (ID <-> EX)
fu_data_t [SUPERSCALAR:0] fu_data_n, fu_data_q;
logic [CVA6Cfg.XLEN-1:0] imm_forward_rs3;
fu_data_t [CVA6Cfg.NrIssuePorts-1:0] fu_data_n, fu_data_q;
logic [ CVA6Cfg.XLEN-1:0] imm_forward_rs3;
logic [ SUPERSCALAR:0] alu_valid_q;
logic [ SUPERSCALAR:0] mult_valid_q;
logic [ SUPERSCALAR:0] fpu_valid_q;
logic [ 1:0] fpu_fmt_q;
logic [ 2:0] fpu_rm_q;
logic [ SUPERSCALAR:0] alu2_valid_q;
logic [ SUPERSCALAR:0] lsu_valid_q;
logic [ SUPERSCALAR:0] csr_valid_q;
logic [ SUPERSCALAR:0] branch_valid_q;
logic [ SUPERSCALAR:0] cvxif_valid_q;
logic [ 31:0] cvxif_off_instr_q;
logic [CVA6Cfg.NrIssuePorts-1:0] alu_valid_q;
logic [CVA6Cfg.NrIssuePorts-1:0] mult_valid_q;
logic [CVA6Cfg.NrIssuePorts-1:0] fpu_valid_q;
logic [ 1:0] fpu_fmt_q;
logic [ 2:0] fpu_rm_q;
logic [CVA6Cfg.NrIssuePorts-1:0] alu2_valid_q;
logic [CVA6Cfg.NrIssuePorts-1:0] lsu_valid_q;
logic [CVA6Cfg.NrIssuePorts-1:0] csr_valid_q;
logic [CVA6Cfg.NrIssuePorts-1:0] branch_valid_q;
logic [CVA6Cfg.NrIssuePorts-1:0] cvxif_valid_q;
logic [ 31:0] cvxif_off_instr_q;
logic [SUPERSCALAR:0][31:0] tinst_n, tinst_q; // transformed instruction
logic [CVA6Cfg.NrIssuePorts-1:0][31:0] tinst_n, tinst_q; // transformed instruction
// forwarding signals
logic [SUPERSCALAR:0] forward_rs1, forward_rs2, forward_rs3;
logic [CVA6Cfg.NrIssuePorts-1:0] forward_rs1, forward_rs2, forward_rs3;
// original instruction
riscv::instruction_t orig_instr;
@ -160,7 +160,7 @@ module issue_read_operands
// ID <-> EX registers
for (genvar i = 0; i <= SUPERSCALAR; i++) begin
for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
assign rs1_forwarding_o[i] = fu_data_n[i].operand_a[CVA6Cfg.VLEN-1:0]; //forwarding or unregistered rs1 value
assign rs2_forwarding_o[i] = fu_data_n[i].operand_b[CVA6Cfg.VLEN-1:0]; //forwarding or unregistered rs2 value
end
@ -204,7 +204,7 @@ module issue_read_operands
if (CVA6Cfg.FpPresent && !fpu_ready_i) begin
fus_busy[0].fpu = 1'b1;
fus_busy[0].fpu_vec = 1'b1;
if (SUPERSCALAR) fus_busy[0].alu2 = 1'b1;
if (CVA6Cfg.SuperscalarEn) fus_busy[0].alu2 = 1'b1;
end
if (!lsu_ready_i) begin
@ -216,13 +216,13 @@ module issue_read_operands
fus_busy[0].cvxif = 1'b1;
end
if (SUPERSCALAR) begin
if (CVA6Cfg.SuperscalarEn) begin
fus_busy[1] = fus_busy[0];
unique case (issue_instr_i[0].fu)
NONE: fus_busy[1].none = 1'b1;
CTRL_FLOW: begin
if (ariane_pkg::SPECULATIVE_SB) begin
if (CVA6Cfg.SpeculativeSb) begin
// Issue speculative instruction, will be removed on BMISS
fus_busy[1].alu = 1'b1;
fus_busy[1].ctrl_flow = 1'b1;
@ -244,7 +244,7 @@ module issue_read_operands
end
end
ALU: begin
if (SUPERSCALAR && !fus_busy[0].alu2) begin
if (CVA6Cfg.SuperscalarEn && !fus_busy[0].alu2) begin
fus_busy[1].alu2 = 1'b1;
// TODO is there a minimum float execution time?
// If so we could issue FPU & ALU2 the same cycle
@ -277,12 +277,12 @@ module issue_read_operands
// select the right busy signal
// this obviously depends on the functional unit we need
for (genvar i = 0; i <= ariane_pkg::SUPERSCALAR; i++) begin
for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
always_comb begin
unique case (issue_instr_i[i].fu)
NONE: fu_busy[i] = fus_busy[i].none;
ALU: begin
if (SUPERSCALAR && !fus_busy[i].alu2) begin
if (CVA6Cfg.SuperscalarEn && !fus_busy[i].alu2) begin
fu_busy[i] = fus_busy[i].alu2;
end else begin
fu_busy[i] = fus_busy[i].alu;
@ -313,7 +313,7 @@ module issue_read_operands
forward_rs2 = '0;
forward_rs3 = '0; // FPR only
for (int unsigned i = 0; i <= SUPERSCALAR; i++) begin
for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
// poll the scoreboard for those values
rs1_o[i] = issue_instr_i[i].rs1;
rs2_o[i] = issue_instr_i[i].rs2;
@ -370,7 +370,7 @@ module issue_read_operands
end
end
if (SUPERSCALAR) begin
if (CVA6Cfg.SuperscalarEn) begin
if (!issue_instr_i[1].use_zimm && (!CVA6Cfg.FpPresent || (is_rs1_fpr(
issue_instr_i[1].op
) == is_rd_fpr(
@ -408,7 +408,7 @@ module issue_read_operands
end
// Forwarding/Output MUX
for (genvar i = 0; i <= SUPERSCALAR; i++) begin
for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
always_comb begin : forwarding_operand_select
// default is regfiles (gpr or fpr)
fu_data_n[i].operand_a = operand_a_regfile[i];
@ -490,11 +490,11 @@ module issue_read_operands
// Exception pass through:
// If an exception has occurred simply pass it through
// we do not want to issue this instruction
for (int unsigned i = 0; i <= SUPERSCALAR; i++) begin
for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
if (!issue_instr_i[i].ex.valid && issue_instr_valid_i[i] && issue_ack_o[i]) begin
case (issue_instr_i[i].fu)
ALU: begin
if (SUPERSCALAR && !fus_busy[i].alu2) begin
if (CVA6Cfg.SuperscalarEn && !fus_busy[i].alu2) begin
alu2_valid_q[i] <= 1'b1;
end else begin
alu_valid_q[i] <= 1'b1;
@ -548,7 +548,7 @@ module issue_read_operands
end else begin
cvxif_valid_q <= '0;
cvxif_off_instr_q <= 32'b0;
for (int unsigned i = 0; i <= SUPERSCALAR; i++) begin
for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
if (!issue_instr_i[i].ex.valid && issue_instr_valid_i[i] && issue_ack_o[i]) begin
case (issue_instr_i[i].fu)
CVXIF: begin
@ -571,7 +571,7 @@ module issue_read_operands
// destination register.
// We also need to check if there is an unresolved branch in the scoreboard.
always_comb begin : issue_scoreboard
for (int unsigned i = 0; i <= SUPERSCALAR; i++) begin
for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
// default assignment
issue_ack_o[i] = 1'b0;
// check that we didn't stall, that the instruction we got is valid
@ -620,7 +620,7 @@ module issue_read_operands
end
end
if (SUPERSCALAR) begin
if (CVA6Cfg.SuperscalarEn) begin
if (!issue_ack_o[0]) begin
issue_ack_o[1] = 1'b0;
end
@ -638,7 +638,7 @@ module issue_read_operands
logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0] wdata_pack;
logic [CVA6Cfg.NrCommitPorts-1:0] we_pack;
for (genvar i = 0; i <= SUPERSCALAR; i++) begin
for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
assign raddr_pack[i*OPERANDS_PER_INSTR+0] = issue_instr_i[i].rs1[4:0];
assign raddr_pack[i*OPERANDS_PER_INSTR+1] = issue_instr_i[i].rs2[4:0];
if (OPERANDS_PER_INSTR == 3) begin
@ -697,7 +697,7 @@ module issue_read_operands
issue_instr_i[0].result[4:0], issue_instr_i[0].rs2[4:0], issue_instr_i[0].rs1[4:0]
};
if (SUPERSCALAR) begin
if (CVA6Cfg.SuperscalarEn) begin
if (!(issue_instr_i[0].fu inside {FPU, FPU_VEC})) begin
fp_raddr_pack = {
issue_instr_i[1].result[4:0], issue_instr_i[1].rs2[4:0], issue_instr_i[1].rs1[4:0]
@ -753,7 +753,7 @@ module issue_read_operands
assign operand_c_fpr = fprdata[2];
end
for (genvar i = 0; i <= SUPERSCALAR; i++) begin
for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
if (CVA6Cfg.NrRgprPorts == 3) begin : gen_operand_c
assign operand_c_gpr[i] = rdata[i*OPERANDS_PER_INSTR+2];
end
@ -786,7 +786,7 @@ module issue_read_operands
if (CVA6Cfg.RVH) begin
tinst_q <= tinst_n;
end
if (SUPERSCALAR) begin
if (CVA6Cfg.SuperscalarEn) begin
if (issue_instr_i[1].fu == CTRL_FLOW) begin
pc_o <= issue_instr_i[1].pc;
is_compressed_instr_o <= issue_instr_i[1].is_compressed;
@ -803,7 +803,7 @@ module issue_read_operands
//pragma translate_off
initial begin
assert (CVA6Cfg.NrRgprPorts == 2 || (CVA6Cfg.NrRgprPorts == 3 && CVA6Cfg.CvxifEn) || SUPERSCALAR)
assert (OPERANDS_PER_INSTR == 2 || (OPERANDS_PER_INSTR == 3 && CVA6Cfg.CvxifEn))
else
$fatal(
1,
@ -820,12 +820,12 @@ module issue_read_operands
// of ALU2 so that FPU is not busy. However, if FPU has a minimum execution
// time of 2 cycles, it is possible to simply not raise fus_busy[1].alu2.
initial begin
assert (!(SUPERSCALAR && CVA6Cfg.FpPresent))
assert (!(CVA6Cfg.SuperscalarEn && CVA6Cfg.FpPresent))
else
$fatal(1, "FPU is not yet supported in superscalar CVA6, see comments above this assertion.");
end
for (genvar i = 0; i <= SUPERSCALAR; i++) begin
for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
assert property (@(posedge clk_i) (branch_valid_q) |-> (!$isunknown(
fu_data_q[i].operand_a
) && !$isunknown(

72
core/issue_stage.sv
View file

@ -37,57 +37,57 @@ module issue_stage
// Stall inserted by Acc dispatcher - ACC_DISPATCHER
input logic stall_i,
// Handshake's data with decode stage - ID_STAGE
input scoreboard_entry_t [SUPERSCALAR:0] decoded_instr_i,
input scoreboard_entry_t [CVA6Cfg.NrIssuePorts-1:0] decoded_instr_i,
// instruction value - ID_STAGE
input logic [SUPERSCALAR:0][31:0] orig_instr_i,
input logic [CVA6Cfg.NrIssuePorts-1:0][31:0] orig_instr_i,
// Handshake's valid with decode stage - ID_STAGE
input logic [SUPERSCALAR:0] decoded_instr_valid_i,
input logic [CVA6Cfg.NrIssuePorts-1:0] decoded_instr_valid_i,
// Is instruction a control flow instruction - ID_STAGE
input logic [SUPERSCALAR:0] is_ctrl_flow_i,
input logic [CVA6Cfg.NrIssuePorts-1:0] is_ctrl_flow_i,
// Handshake's acknowlege with decode stage - ID_STAGE
output logic [SUPERSCALAR:0] decoded_instr_ack_o,
output logic [CVA6Cfg.NrIssuePorts-1:0] decoded_instr_ack_o,
// rs1 forwarding - EX_STAGE
output [SUPERSCALAR:0][CVA6Cfg.VLEN-1:0] rs1_forwarding_o,
output [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.VLEN-1:0] rs1_forwarding_o,
// rs2 forwarding - EX_STAGE
output [SUPERSCALAR:0][CVA6Cfg.VLEN-1:0] rs2_forwarding_o,
output [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.VLEN-1:0] rs2_forwarding_o,
// FU data useful to execute instruction - EX_STAGE
output fu_data_t [SUPERSCALAR:0] fu_data_o,
output fu_data_t [CVA6Cfg.NrIssuePorts-1:0] fu_data_o,
// Program Counter - EX_STAGE
output logic [CVA6Cfg.VLEN-1:0] pc_o,
// Is compressed instruction - EX_STAGE
output logic is_compressed_instr_o,
// Transformed trap instruction - EX_STAGE
output logic [SUPERSCALAR:0][31:0] tinst_o,
output logic [CVA6Cfg.NrIssuePorts-1:0][31:0] tinst_o,
// Fixed Latency Unit is ready - EX_STAGE
input logic flu_ready_i,
// ALU FU is valid - EX_STAGE
output logic [SUPERSCALAR:0] alu_valid_o,
output logic [CVA6Cfg.NrIssuePorts-1:0] alu_valid_o,
// Signaling that we resolved the branch - EX_STAGE
input logic resolve_branch_i,
// Load store unit FU is ready - EX_STAGE
input logic lsu_ready_i,
// Load store unit FU is valid - EX_STAGE
output logic [SUPERSCALAR:0] lsu_valid_o,
output logic [CVA6Cfg.NrIssuePorts-1:0] lsu_valid_o,
// Branch unit is valid - EX_STAGE
output logic [SUPERSCALAR:0] branch_valid_o,
output logic [CVA6Cfg.NrIssuePorts-1:0] branch_valid_o,
// Information of branch prediction - EX_STAGE
output branchpredict_sbe_t branch_predict_o,
// Mult FU is valid - EX_STAGE
output logic [SUPERSCALAR:0] mult_valid_o,
output logic [CVA6Cfg.NrIssuePorts-1:0] mult_valid_o,
// FPU FU is ready - EX_STAGE
input logic fpu_ready_i,
// FPU FU is valid - EX_STAGE
output logic [SUPERSCALAR:0] fpu_valid_o,
output logic [CVA6Cfg.NrIssuePorts-1:0] fpu_valid_o,
// FPU fmt field - EX_STAGE
output logic [1:0] fpu_fmt_o,
// FPU rm field - EX_STAGE
output logic [2:0] fpu_rm_o,
// ALU2 FU is valid - EX_STAGE
output logic [SUPERSCALAR:0] alu2_valid_o,
output logic [CVA6Cfg.NrIssuePorts-1:0] alu2_valid_o,
// CSR is valid - EX_STAGE
output logic [SUPERSCALAR:0] csr_valid_o,
output logic [CVA6Cfg.NrIssuePorts-1:0] csr_valid_o,
// CVXIF FU is valid - EX_STAGE
output logic [SUPERSCALAR:0] x_issue_valid_o,
output logic [CVA6Cfg.NrIssuePorts-1:0] x_issue_valid_o,
// CVXIF is FU ready - EX_STAGE
input logic x_issue_ready_i,
// CVXIF offloader instruction value - EX_STAGE
@ -125,7 +125,7 @@ module issue_stage
// Issue stall - PERF_COUNTERS
output logic stall_issue_o,
// Information dedicated to RVFI - RVFI
output logic [SUPERSCALAR:0][CVA6Cfg.TRANS_ID_BITS-1:0] rvfi_issue_pointer_o,
output logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] rvfi_issue_pointer_o,
// Information dedicated to RVFI - RVFI
output logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] rvfi_commit_pointer_o
);
@ -134,30 +134,30 @@ module issue_stage
// ---------------------------------------------------
typedef logic [(CVA6Cfg.NrRgprPorts == 3 ? CVA6Cfg.XLEN : CVA6Cfg.FLen)-1:0] rs3_len_t;
fu_t [2**REG_ADDR_SIZE-1:0] rd_clobber_gpr_sb_iro;
fu_t [2**REG_ADDR_SIZE-1:0] rd_clobber_fpr_sb_iro;
fu_t [ 2**REG_ADDR_SIZE-1:0] rd_clobber_gpr_sb_iro;
fu_t [ 2**REG_ADDR_SIZE-1:0] rd_clobber_fpr_sb_iro;
logic [ SUPERSCALAR:0][REG_ADDR_SIZE-1:0] rs1_iro_sb;
logic [ SUPERSCALAR:0][ CVA6Cfg.XLEN-1:0] rs1_sb_iro;
logic [ SUPERSCALAR:0] rs1_valid_sb_iro;
logic [CVA6Cfg.NrIssuePorts-1:0][REG_ADDR_SIZE-1:0] rs1_iro_sb;
logic [CVA6Cfg.NrIssuePorts-1:0][ CVA6Cfg.XLEN-1:0] rs1_sb_iro;
logic [CVA6Cfg.NrIssuePorts-1:0] rs1_valid_sb_iro;
logic [ SUPERSCALAR:0][REG_ADDR_SIZE-1:0] rs2_iro_sb;
logic [ SUPERSCALAR:0][ CVA6Cfg.XLEN-1:0] rs2_sb_iro;
logic [ SUPERSCALAR:0] rs2_valid_iro_sb;
logic [CVA6Cfg.NrIssuePorts-1:0][REG_ADDR_SIZE-1:0] rs2_iro_sb;
logic [CVA6Cfg.NrIssuePorts-1:0][ CVA6Cfg.XLEN-1:0] rs2_sb_iro;
logic [CVA6Cfg.NrIssuePorts-1:0] rs2_valid_iro_sb;
logic [ SUPERSCALAR:0][REG_ADDR_SIZE-1:0] rs3_iro_sb;
rs3_len_t [ SUPERSCALAR:0] rs3_sb_iro;
logic [ SUPERSCALAR:0] rs3_valid_iro_sb;
logic [CVA6Cfg.NrIssuePorts-1:0][REG_ADDR_SIZE-1:0] rs3_iro_sb;
rs3_len_t [CVA6Cfg.NrIssuePorts-1:0] rs3_sb_iro;
logic [CVA6Cfg.NrIssuePorts-1:0] rs3_valid_iro_sb;
scoreboard_entry_t [ SUPERSCALAR:0] issue_instr_sb_iro;
logic [ SUPERSCALAR:0][ 31:0] orig_instr_sb_iro;
logic [ SUPERSCALAR:0] issue_instr_valid_sb_iro;
logic [ SUPERSCALAR:0] issue_ack_iro_sb;
scoreboard_entry_t [CVA6Cfg.NrIssuePorts-1:0] issue_instr_sb_iro;
logic [CVA6Cfg.NrIssuePorts-1:0][ 31:0] orig_instr_sb_iro;
logic [CVA6Cfg.NrIssuePorts-1:0] issue_instr_valid_sb_iro;
logic [CVA6Cfg.NrIssuePorts-1:0] issue_ack_iro_sb;
logic [ SUPERSCALAR:0][ CVA6Cfg.XLEN-1:0] rs1_forwarding_xlen;
logic [ SUPERSCALAR:0][ CVA6Cfg.XLEN-1:0] rs2_forwarding_xlen;
logic [CVA6Cfg.NrIssuePorts-1:0][ CVA6Cfg.XLEN-1:0] rs1_forwarding_xlen;
logic [CVA6Cfg.NrIssuePorts-1:0][ CVA6Cfg.XLEN-1:0] rs2_forwarding_xlen;
for (genvar i = 0; i <= SUPERSCALAR; i++) begin
for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
assign rs1_forwarding_o[i] = rs1_forwarding_xlen[i][CVA6Cfg.VLEN-1:0];
assign rs2_forwarding_o[i] = rs2_forwarding_xlen[i][CVA6Cfg.VLEN-1:0];
end

14
core/load_store_unit.sv
View file

@ -135,18 +135,18 @@ module load_store_unit
output logic dtlb_miss_o,
// Data cache request output - CACHES
input dcache_req_o_t [ 2:0] dcache_req_ports_i,
input dcache_req_o_t [2:0] dcache_req_ports_i,
// Data cache request input - CACHES
output dcache_req_i_t [ 2:0] dcache_req_ports_o,
output dcache_req_i_t [2:0] dcache_req_ports_o,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic dcache_wbuffer_empty_i,
input logic dcache_wbuffer_empty_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic dcache_wbuffer_not_ni_i,
input logic dcache_wbuffer_not_ni_i,
// AMO request - CACHE
output amo_req_t amo_req_o,
output amo_req_t amo_req_o,
// AMO response - CACHE
input amo_resp_t amo_resp_i,
input amo_resp_t amo_resp_i,
// PMP configuration - CSR_REGFILE
input riscv::pmpcfg_t [CVA6Cfg.NrPMPEntries:0] pmpcfg_i,
// PMP address - CSR_REGFILE

68
core/scoreboard.sv
View file

@ -35,25 +35,25 @@ module scoreboard #(
output ariane_pkg::fu_t [2**ariane_pkg::REG_ADDR_SIZE-1:0] rd_clobber_fpr_o,
// rs1 operand address - issue_read_operands
input logic [ariane_pkg::SUPERSCALAR:0][ariane_pkg::REG_ADDR_SIZE-1:0] rs1_i,
input logic [CVA6Cfg.NrIssuePorts-1:0][ariane_pkg::REG_ADDR_SIZE-1:0] rs1_i,
// rs1 operand - issue_read_operands
output logic [ariane_pkg::SUPERSCALAR:0][ CVA6Cfg.XLEN-1:0] rs1_o,
output logic [CVA6Cfg.NrIssuePorts-1:0][ CVA6Cfg.XLEN-1:0] rs1_o,
// rs1 operand is valid - issue_read_operands
output logic [ariane_pkg::SUPERSCALAR:0] rs1_valid_o,
output logic [CVA6Cfg.NrIssuePorts-1:0] rs1_valid_o,
// rs2 operand address - issue_read_operands
input logic [ariane_pkg::SUPERSCALAR:0][ariane_pkg::REG_ADDR_SIZE-1:0] rs2_i,
input logic [CVA6Cfg.NrIssuePorts-1:0][ariane_pkg::REG_ADDR_SIZE-1:0] rs2_i,
// rs2 operand - issue_read_operands
output logic [ariane_pkg::SUPERSCALAR:0][ CVA6Cfg.XLEN-1:0] rs2_o,
output logic [CVA6Cfg.NrIssuePorts-1:0][ CVA6Cfg.XLEN-1:0] rs2_o,
// rs2 operand is valid - issue_read_operands
output logic [ariane_pkg::SUPERSCALAR:0] rs2_valid_o,
output logic [CVA6Cfg.NrIssuePorts-1:0] rs2_valid_o,
// rs3 operand address - issue_read_operands
input logic [ariane_pkg::SUPERSCALAR:0][ariane_pkg::REG_ADDR_SIZE-1:0] rs3_i,
input logic [CVA6Cfg.NrIssuePorts-1:0][ariane_pkg::REG_ADDR_SIZE-1:0] rs3_i,
// rs3 operand - issue_read_operands
output rs3_len_t [ariane_pkg::SUPERSCALAR:0] rs3_o,
output rs3_len_t [CVA6Cfg.NrIssuePorts-1:0] rs3_o,
// rs3 operand is valid - issue_read_operands
output logic [ariane_pkg::SUPERSCALAR:0] rs3_valid_o,
output logic [CVA6Cfg.NrIssuePorts-1:0] rs3_valid_o,
// advertise instruction to commit stage, if commit_ack_i is asserted advance the commit pointer
// TO_BE_COMPLETED - TO_BE_COMPLETED
@ -66,23 +66,23 @@ module scoreboard #(
// instruction to put on top of scoreboard e.g.: top pointer
// we can always put this instruction to the top unless we signal with asserted full_o
// TO_BE_COMPLETED - TO_BE_COMPLETED
input scoreboard_entry_t [ariane_pkg::SUPERSCALAR:0] decoded_instr_i,
input scoreboard_entry_t [CVA6Cfg.NrIssuePorts-1:0] decoded_instr_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic [ariane_pkg::SUPERSCALAR:0][31:0] orig_instr_i,
input logic [CVA6Cfg.NrIssuePorts-1:0][31:0] orig_instr_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic [ariane_pkg::SUPERSCALAR:0] decoded_instr_valid_i,
input logic [CVA6Cfg.NrIssuePorts-1:0] decoded_instr_valid_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
output logic [ariane_pkg::SUPERSCALAR:0] decoded_instr_ack_o,
output logic [CVA6Cfg.NrIssuePorts-1:0] decoded_instr_ack_o,
// instruction to issue logic, if issue_instr_valid and issue_ready is asserted, advance the issue pointer
// Issue scoreboard entry - ACC_DISPATCHER
output scoreboard_entry_t [ariane_pkg::SUPERSCALAR:0] issue_instr_o,
output scoreboard_entry_t [CVA6Cfg.NrIssuePorts-1:0] issue_instr_o,
// TO_BE_COMPLETED - TO_BE_COMPLETED
output logic [ariane_pkg::SUPERSCALAR:0][31:0] orig_instr_o,
output logic [CVA6Cfg.NrIssuePorts-1:0][31:0] orig_instr_o,
// TO_BE_COMPLETED - TO_BE_COMPLETED
output logic [ariane_pkg::SUPERSCALAR:0] issue_instr_valid_o,
output logic [CVA6Cfg.NrIssuePorts-1:0] issue_instr_valid_o,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input logic [ariane_pkg::SUPERSCALAR:0] issue_ack_i,
input logic [CVA6Cfg.NrIssuePorts-1:0] issue_ack_i,
// TO_BE_COMPLETED - TO_BE_COMPLETED
input bp_resolve_t resolved_branch_i,
@ -98,7 +98,7 @@ module scoreboard #(
input logic x_we_i,
// TO_BE_COMPLETED - RVFI
output logic [ariane_pkg::SUPERSCALAR:0][CVA6Cfg.TRANS_ID_BITS-1:0] rvfi_issue_pointer_o,
output logic [ CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] rvfi_issue_pointer_o,
// TO_BE_COMPLETED - RVFI
output logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] rvfi_commit_pointer_o
);
@ -113,16 +113,16 @@ module scoreboard #(
sb_mem_t [CVA6Cfg.NR_SB_ENTRIES-1:0] mem_q, mem_n;
logic [CVA6Cfg.NR_SB_ENTRIES-1:0] still_issued;
logic [ariane_pkg::SUPERSCALAR:0] issue_full;
logic [CVA6Cfg.NrIssuePorts-1:0] issue_full;
logic [1:0][CVA6Cfg.NR_SB_ENTRIES/2-1:0] issued_instrs_even_odd;
logic bmiss;
logic [CVA6Cfg.TRANS_ID_BITS-1:0] after_flu_wb;
logic [CVA6Cfg.NR_SB_ENTRIES-1:0] speculative_instrs;
logic [ariane_pkg::SUPERSCALAR:0] num_issue;
logic [CVA6Cfg.NrIssuePorts-1:0] num_issue;
logic [CVA6Cfg.TRANS_ID_BITS-1:0] issue_pointer_n, issue_pointer_q;
logic [ariane_pkg::SUPERSCALAR+1:0][CVA6Cfg.TRANS_ID_BITS-1:0] issue_pointer;
logic [CVA6Cfg.NrIssuePorts:0][CVA6Cfg.TRANS_ID_BITS-1:0] issue_pointer;
logic [CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.TRANS_ID_BITS-1:0] commit_pointer_n, commit_pointer_q;
logic [$clog2(CVA6Cfg.NrCommitPorts):0] num_commit;
@ -137,7 +137,7 @@ module scoreboard #(
// the issue queue is full don't issue any new instructions
assign issue_full[0] = &issued_instrs_even_odd[0] && &issued_instrs_even_odd[1];
if (ariane_pkg::SUPERSCALAR) begin : assign_issue_full
if (CVA6Cfg.SuperscalarEn) begin : assign_issue_full
// Need two slots available to issue two instructions.
// They are next to each other so one must be even and one odd
assign issue_full[1] = &issued_instrs_even_odd[0] || &issued_instrs_even_odd[1];
@ -155,7 +155,7 @@ module scoreboard #(
end
assign issue_pointer[0] = issue_pointer_q;
for (genvar i = 0; i <= ariane_pkg::SUPERSCALAR; i++) begin
for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
assign issue_pointer[i+1] = issue_pointer[i] + 'd1;
end
@ -164,7 +164,7 @@ module scoreboard #(
decoded_instr_ack_o = '0;
issue_instr_o = decoded_instr_i;
orig_instr_o = orig_instr_i;
for (int unsigned i = 0; i <= ariane_pkg::SUPERSCALAR; i++) begin
for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
// make sure we assign the correct trans ID
issue_instr_o[i].trans_id = issue_pointer[i];
@ -181,7 +181,7 @@ module scoreboard #(
num_issue = '0;
// if we got a acknowledge from the issue stage, put this scoreboard entry in the queue
for (int unsigned i = 0; i <= ariane_pkg::SUPERSCALAR; i++) begin
for (int unsigned i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
if (decoded_instr_valid_i[i] && decoded_instr_ack_o[i] && !flush_unissued_instr_i) begin
// the decoded instruction we put in there is valid (1st bit)
// increase the issue counter and advance issue pointer
@ -240,7 +240,7 @@ module scoreboard #(
// ------------
// Cancel
// ------------
if (ariane_pkg::SPECULATIVE_SB) begin
if (CVA6Cfg.SpeculativeSb) begin
if (bmiss) begin
for (int unsigned i = 0; i < CVA6Cfg.NR_SB_ENTRIES; i++) begin
if (speculative_instrs[i]) begin
@ -280,7 +280,7 @@ module scoreboard #(
assign bmiss = resolved_branch_i.valid && resolved_branch_i.is_mispredict;
assign after_flu_wb = trans_id_i[ariane_pkg::FLU_WB] + 'd1;
if (ariane_pkg::SPECULATIVE_SB) begin : find_speculative_instrs
if (CVA6Cfg.SpeculativeSb) begin : find_speculative_instrs
round_interval #(
.S(CVA6Cfg.TRANS_ID_BITS)
) i_speculative_instrs (
@ -385,13 +385,13 @@ module scoreboard #(
// Read Operands (a.k.a forwarding)
// ----------------------------------
// read operand interface: same logic as register file
logic [ariane_pkg::SUPERSCALAR:0][CVA6Cfg.NR_SB_ENTRIES+CVA6Cfg.NrWbPorts-1:0]
logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.NR_SB_ENTRIES+CVA6Cfg.NrWbPorts-1:0]
rs1_fwd_req, rs2_fwd_req, rs3_fwd_req;
logic [ariane_pkg::SUPERSCALAR:0][CVA6Cfg.NR_SB_ENTRIES+CVA6Cfg.NrWbPorts-1:0][CVA6Cfg.XLEN-1:0] rs_data;
logic [ariane_pkg::SUPERSCALAR:0] rs1_valid, rs2_valid, rs3_valid;
logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.NR_SB_ENTRIES+CVA6Cfg.NrWbPorts-1:0][CVA6Cfg.XLEN-1:0] rs_data;
logic [CVA6Cfg.NrIssuePorts-1:0] rs1_valid, rs2_valid, rs3_valid;
// WB ports have higher prio than entries
for (genvar i = 0; i <= ariane_pkg::SUPERSCALAR; i++) begin
for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
for (genvar k = 0; unsigned'(k) < CVA6Cfg.NrWbPorts; k++) begin : gen_rs_wb
assign rs1_fwd_req[i][k] = (mem_q[trans_id_i[k]].sbe.rd == rs1_i[i]) & (~mem_q[trans_id_i[k]].cancelled) & wt_valid_i[k] & (~ex_i[k].valid) & (mem_q[trans_id_i[k]].is_rd_fpr_flag == (CVA6Cfg.FpPresent && ariane_pkg::is_rs1_fpr(
issue_instr_o[i].op
@ -468,7 +468,7 @@ module scoreboard #(
.idx_o ()
);
logic [ariane_pkg::SUPERSCALAR:0][CVA6Cfg.XLEN-1:0] rs3;
logic [CVA6Cfg.NrIssuePorts-1:0][CVA6Cfg.XLEN-1:0] rs3;
rr_arb_tree #(
.NumIn(CVA6Cfg.NR_SB_ENTRIES + CVA6Cfg.NrWbPorts),
@ -511,7 +511,7 @@ module scoreboard #(
end
//RVFI
assign rvfi_issue_pointer_o = issue_pointer[ariane_pkg::SUPERSCALAR:0];
assign rvfi_issue_pointer_o = issue_pointer[CVA6Cfg.NrIssuePorts-1:0];
assign rvfi_commit_pointer_o = commit_pointer_q;
//pragma translate_off
@ -533,7 +533,7 @@ module scoreboard #(
else $fatal(1, "Commit acknowledged but instruction is not valid");
end
// assert that we never give an issue ack signal if the instruction is not valid
for (genvar i = 0; i <= ariane_pkg::SUPERSCALAR; i++) begin
for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin
assert property (
@(posedge clk_i) disable iff (!rst_ni) issue_ack_i[i] |-> issue_instr_valid_o[i])
else $fatal(1, "Issue acknowledged but instruction is not valid");