github-mirrors/cva6
1
0
Fork 0
mirror of https://github.com/openhwgroup/cva6.git synced 2025-04-20 04:07:36 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

Misc fixes related to openpiton compilation

Browse source
This commit is contained in:
Michael Schaffner 2018-10-29 09:22:35 +01:00
parent 8a10998f9d
commit 5060b99508
No known key found for this signature in database
GPG key ID: 7AA09AE049819C2C
9 changed files with 70 additions and 66 deletions
Download patch file Download diff file Expand all files Collapse all files

7
Flist.ariane
View file

@ -15,8 +15,6 @@
// Author: Michael Schaffner <schaffner@iis.ee.ethz.ch>, ETH Zurich
// Date: 15.08.2018
// Description: File list for OpenPiton flow
+define+SERPENT_PULP
// src/fpu_div_sqrt_mvp/hdl/fpu_ff.sv
// src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
// src/fpu_div_sqrt_mvp/hdl/control_mvp.sv
@ -51,13 +49,14 @@
// src/fpu/src/subunits/conv_block.vhd
// src/fpu/src/fpnew.vhd
// src/fpu/src/fpnew_top.vhd
src/axi/src/axi_pkg.sv
src/debug/dm_pkg.sv
include/riscv_pkg.sv
include/ariane_pkg.sv
include/ariane_axi_pkg.sv
include/serpent_cache_pkg.sv
include/std_cache_pkg.sv
//include/std_cache_pkg.sv
include/axi_intf.sv
src/debug/dm_pkg.sv
src/util/instruction_tracer_pkg.sv
src/util/instruction_tracer_if.sv
src/util/sram.sv

4
include/ariane_axi_pkg.sv
View file

@ -16,6 +16,10 @@
*/
package ariane_axi;
// used in axi_adapter.sv
typedef enum logic { SINGLE_REQ, CACHE_LINE_REQ } ad_req_t;
// 4 is recommended by AXI standard, so lets stick to it, do not change
localparam IdWidth = 4;
localparam UserWidth = 1;

2
include/serpent_cache_pkg.sv
View file

@ -21,7 +21,7 @@ package serpent_cache_pkg;
// these parames need to coincide with the current L1.5 parameterization
// do not change
localparam L15_SET_ASSOC = 4;
localparam L15_TID_WIDTH = 2;
localparam L15_TID_WIDTH = 1;
localparam L15_TLB_CSM_WIDTH = 33;
localparam L15_WAY_WIDTH = $clog2(L15_SET_ASSOC);

3
include/std_cache_pkg.sv
View file

@ -25,9 +25,6 @@ package std_cache_pkg;
localparam DCACHE_DIRTY_WIDTH = ariane_pkg::DCACHE_SET_ASSOC*2;
// localparam DECISION_BIT = 30; // bit on which to decide whether the request is cache-able or not
typedef enum logic { SINGLE_REQ, CACHE_LINE_REQ } req_t;
typedef struct packed {
logic [1:0] id; // id for which we handle the miss
logic valid;

67
src/ariane.sv
View file

@ -713,6 +713,40 @@ module ariane #(
it.close();
end
endprogram
`ifdef SERPENT_PULP
logic piton_pc_vld;
logic [63:0] piton_pc;
// expose retired PCs to OpenPiton verification environment
// note: this only works with single issue, need to adapt this in case of dual issue
always_ff @(posedge clk_i or negedge rst_ni) begin
logic [63:0] pc_queue [$];
if (~rst_ni) begin
pc_queue.delete();
piton_pc_vld <= 1'b0;
piton_pc <= '0;
end else begin
// serialize retired PCs via queue construct
for (int i = 0; i < NR_COMMIT_PORTS; i++) begin
if (commit_ack[i] && !commit_instr_id_commit[i].ex.valid) begin
pc_queue.push_back(commit_instr_id_commit[i].pc);
end
end
if (pc_queue.size()>0) begin
piton_pc_vld <= 1'b1;
piton_pc <= pc_queue.pop_front();
end else begin
piton_pc_vld <= 1'b0;
piton_pc <= '0;
end
end
end
`endif // SERPENT_PULP
// mock tracer for Verilator, to be used with spike-dasm
`else
@ -758,39 +792,6 @@ module ariane #(
final begin
$fclose(f);
end
`ifdef SERPENT_PULP
logic piton_pc_vld;
logic [63:0] piton_pc;
// expose retired PCs to OpenPiton verification environment
// note: this only works with single issue, need to adapt this in case of dual issue
always_ff @(posedge clk_i or negedge rst_ni) begin
logic [63:0] pc_queue [$];
if (~rst_ni) begin
pc_queue.delete();
piton_pc_vld <= 1'b0;
piton_pc <= '0;
end else begin
// serialize retired PCs via queue construct
for (int i = 0; i < NR_COMMIT_PORTS; i++) begin
if (commit_ack[i] && !commit_instr_id_commit[i].ex.valid) begin
pc_queue.push_back(commit_instr_id_commit[i].pc);
end
end
if (pc_queue.size()>0) begin
piton_pc_vld <= 1'b1;
piton_pc <= pc_queue.pop_front();
end else begin
piton_pc_vld <= 1'b0;
piton_pc <= '0;
end
end
end
`endif // SERPENT_PULP
`endif // VERILATOR
//pragma translate_on

4
src/ariane_verilog_wrap.sv
View file

@ -26,7 +26,7 @@ module ariane_verilog_wrap #(
parameter logic [63:0] CACHE_START_ADDR = 64'h8000_0000 // address on which to decide whether the request is cache-able or not
) (
input clk_i,
input rst_ni,
input reset_l, // this is an openpiton-specific name, do not change (hier. paths in TB use this)
// Core ID, Cluster ID and boot address are considered more or less static
input [63:0] boot_addr_i, // reset boot address
input [63:0] hart_id_i, // hart id in a multicore environment (reflected in a CSR)
@ -70,7 +70,7 @@ module ariane_verilog_wrap #(
.CACHE_START_ADDR ( CACHE_START_ADDR )
) ariane (
.clk_i ,
.rst_ni ,
.rst_ni ( reset_l ),
.boot_addr_i ,
.hart_id_i ,
.irq_i ,

27
src/axi_adapter.sv
View file

@ -14,18 +14,19 @@
*
* Description: Manages communication with the AXI Bus
*/
import std_cache_pkg::*;
//import std_cache_pkg::*;
module axi_adapter #(
parameter int unsigned DATA_WIDTH = 256,
parameter logic CRITICAL_WORD_FIRST = 0, // the AXI subsystem needs to support wrapping reads for this feature
parameter int unsigned AXI_ID_WIDTH = 10
parameter int unsigned DATA_WIDTH = 256,
parameter logic CRITICAL_WORD_FIRST = 0, // the AXI subsystem needs to support wrapping reads for this feature
parameter int unsigned AXI_ID_WIDTH = 10,
parameter int unsigned CACHELINE_BYTE_OFFSET = 8
)(
input logic clk_i, // Clock
input logic rst_ni, // Asynchronous reset active low
input logic req_i,
input req_t type_i,
input ariane_axi::ad_req_t type_i,
output logic gnt_o,
output logic [AXI_ID_WIDTH-1:0] gnt_id_o,
input logic [63:0] addr_i,
@ -69,7 +70,7 @@ module axi_adapter #(
axi_req_o.aw.region = 4'b0;
axi_req_o.aw.len = 8'b0;
axi_req_o.aw.size = {1'b0, size_i};
axi_req_o.aw.burst = (type_i == SINGLE_REQ) ? 2'b00 : 2'b01; // fixed size for single request and incremental transfer for everything else
axi_req_o.aw.burst = (type_i == ariane_axi::SINGLE_REQ) ? 2'b00 : 2'b01; // fixed size for single request and incremental transfer for everything else
axi_req_o.aw.lock = 1'b0;
axi_req_o.aw.cache = 4'b0;
axi_req_o.aw.qos = 4'b0;
@ -79,12 +80,12 @@ module axi_adapter #(
axi_req_o.ar_valid = 1'b0;
// in case of a single request or wrapping transfer we can simply begin at the address, if we want to request a cache-line
// with an incremental transfer we need to output the corresponding base address of the cache line
axi_req_o.ar.addr = (CRITICAL_WORD_FIRST || type_i == SINGLE_REQ) ? addr_i : { addr_i[63:DCACHE_BYTE_OFFSET], {{DCACHE_BYTE_OFFSET}{1'b0}}};
axi_req_o.ar.addr = (CRITICAL_WORD_FIRST || type_i == ariane_axi::SINGLE_REQ) ? addr_i : { addr_i[63:CACHELINE_BYTE_OFFSET], {{CACHELINE_BYTE_OFFSET}{1'b0}}};
axi_req_o.ar.prot = 3'b0;
axi_req_o.ar.region = 4'b0;
axi_req_o.ar.len = 8'b0;
axi_req_o.ar.size = {1'b0, size_i}; // 8 bytes
axi_req_o.ar.burst = (type_i == SINGLE_REQ) ? 2'b00 : (CRITICAL_WORD_FIRST ? 2'b10 : 2'b01); // wrapping transfer in case of a critical word first strategy
axi_req_o.ar.burst = (type_i == ariane_axi::SINGLE_REQ) ? 2'b00 : (CRITICAL_WORD_FIRST ? 2'b10 : 2'b01); // wrapping transfer in case of a critical word first strategy
axi_req_o.ar.lock = 1'b0;
axi_req_o.ar.cache = 4'b0;
axi_req_o.ar.qos = 4'b0;
@ -127,7 +128,7 @@ module axi_adapter #(
axi_req_o.aw_valid = 1'b1;
axi_req_o.w_valid = 1'b1;
// its a single write
if (type_i == SINGLE_REQ) begin
if (type_i == ariane_axi::SINGLE_REQ) begin
// only a single write so the data is already the last one
axi_req_o.w.last = 1'b1;
// single req can be granted here
@ -162,13 +163,13 @@ module axi_adapter #(
axi_req_o.ar_valid = 1'b1;
gnt_o = axi_resp_i.ar_ready;
if (type_i != SINGLE_REQ) begin
if (type_i != ariane_axi::SINGLE_REQ) begin
axi_req_o.ar.len = BURST_SIZE;
cnt_d = BURST_SIZE;
end
if (axi_resp_i.ar_ready) begin
state_d = (type_i == SINGLE_REQ) ? WAIT_R_VALID : WAIT_R_VALID_MULTIPLE;
state_d = (type_i == ariane_axi::SINGLE_REQ) ? WAIT_R_VALID : WAIT_R_VALID_MULTIPLE;
addr_offset_d = addr_i[ADDR_INDEX-1+3:3];
end
end
@ -189,7 +190,7 @@ module axi_adapter #(
WAIT_LAST_W_READY_AW_READY: begin
axi_req_o.w_valid = 1'b1;
axi_req_o.w.last = (cnt_q == '0);
if (type_i == SINGLE_REQ) begin
if (type_i == ariane_axi::SINGLE_REQ) begin
axi_req_o.w.data = wdata_i[0];
axi_req_o.w.strb = be_i[0];
end else begin
@ -241,7 +242,7 @@ module axi_adapter #(
WAIT_LAST_W_READY: begin
axi_req_o.w_valid = 1'b1;
if (type_i != SINGLE_REQ) begin
if (type_i != ariane_axi::SINGLE_REQ) begin
axi_req_o.w.data = wdata_i[BURST_SIZE-cnt_q];
axi_req_o.w.strb = be_i[BURST_SIZE-cnt_q];
end

20
src/cache_subsystem/miss_handler.sv
View file

@ -104,7 +104,7 @@ module miss_handler #(
logic [DCACHE_LINE_WIDTH-1:0] req_fsm_miss_wdata;
logic req_fsm_miss_we;
logic [(DCACHE_LINE_WIDTH/8)-1:0] req_fsm_miss_be;
req_t req_fsm_miss_req;
ariane_axi::ad_req_t req_fsm_miss_req;
logic [1:0] req_fsm_miss_size;
logic gnt_miss_fsm;
@ -153,7 +153,7 @@ module miss_handler #(
req_fsm_miss_wdata = '0;
req_fsm_miss_we = 1'b0;
req_fsm_miss_be = '0;
req_fsm_miss_req = CACHE_LINE_REQ;
req_fsm_miss_req = ariane_axi::CACHE_LINE_REQ;
req_fsm_miss_size = 2'b11;
// core
flush_ack_o = 1'b0;
@ -385,7 +385,7 @@ module miss_handler #(
req_fsm_miss_valid = 1'b1;
// address is in operand a
req_fsm_miss_addr = amo_req_i.operand_a;
req_fsm_miss_req = SINGLE_REQ;
req_fsm_miss_req = ariane_axi::SINGLE_REQ;
req_fsm_miss_size = amo_req_i.size;
// the request has been granted
if (gnt_miss_fsm) begin
@ -418,7 +418,7 @@ module miss_handler #(
req_fsm_miss_valid = (amo_req_i.amo_op == AMO_LR) ? 1'b0 : 1'b1;
// for a load reserved we do not want to write
req_fsm_miss_we = (amo_req_i.amo_op == AMO_LR) ? 1'b0 : 1'b1;
req_fsm_miss_req = SINGLE_REQ;
req_fsm_miss_req = ariane_axi::SINGLE_REQ;
req_fsm_miss_size = amo_req_i.size;
req_fsm_miss_addr = amo_req_i.operand_a;
@ -550,13 +550,14 @@ module miss_handler #(
);
axi_adapter #(
.DATA_WIDTH ( 64 ),
.AXI_ID_WIDTH ( 4 )
.DATA_WIDTH ( 64 ),
.AXI_ID_WIDTH ( 4 ),
.CACHELINE_BYTE_OFFSET ( DCACHE_BYTE_OFFSET )
) i_bypass_axi_adapter (
.clk_i,
.rst_ni,
.req_i ( req_fsm_bypass_valid ),
.type_i ( SINGLE_REQ ),
.type_i ( ariane_axi::SINGLE_REQ ),
.gnt_o ( gnt_bypass_fsm ),
.addr_i ( req_fsm_bypass_addr ),
.we_i ( req_fsm_bypass_we ),
@ -578,8 +579,9 @@ module miss_handler #(
// Cache Line AXI Refill
// ----------------------
axi_adapter #(
.DATA_WIDTH ( DCACHE_LINE_WIDTH ),
.AXI_ID_WIDTH ( 4 )
.DATA_WIDTH ( DCACHE_LINE_WIDTH ),
.AXI_ID_WIDTH ( 4 ),
.CACHELINE_BYTE_OFFSET ( DCACHE_BYTE_OFFSET )
) i_miss_axi_adapter (
.clk_i,
.rst_ni,

2
src/debug/dm_sba.sv
View file

@ -137,7 +137,7 @@ module dm_sba (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.req_i ( req ),
.type_i ( std_cache_pkg::SINGLE_REQ ),
.type_i ( ariane_axi::SINGLE_REQ ),
.gnt_o ( gnt ),
.gnt_id_o ( ),
.addr_i ( address ),