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WIP: Start debug integration, connect PC gen

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This commit is contained in:
Florian Zaruba 2017-07-19 11:52:05 +02:00
parent e35b65ec1a
commit 52794c87be
2 changed files with 52 additions and 2 deletions
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47
src/ariane.sv
View file

@ -237,6 +237,23 @@ module ariane
logic halt_ctrl_commit;
logic halt_debug_ctrl;
logic halt_csr_ctrl;
// --------------
// Debug <-> *
// --------------
logic [63:0] pc_debug_pcgen;
logic set_pc_debug_pcgen;
logic gpr_req_debug_issue;
logic [4:0] gpr_addr_debug_issue;
logic gpr_we_debug_issue;
logic [63:0] gpr_wdata_debug_issue;
logic [63:0] gpr_rdata_debug_issue;
logic csr_req_debug_csr;
logic [11:0] csr_addr_debug_csr;
logic csr_we_debug_csr;
logic [63:0] csr_wdata_debug_csr;
logic [63:0] csr_rdata_debug_csr;
assign sec_lvl_o = priv_lvl;
// --------------
@ -257,6 +274,8 @@ module ariane
.eret_i ( eret ),
.trap_vector_base_i ( trap_vector_base_commit_pcgen ),
.ex_valid_i ( ex_commit.valid ),
.debug_pc_i ( pc_debug_pcgen ),
.debug_set_pc_i ( set_pc_debug_pcgen ),
.*
);
// ---------
@ -509,7 +528,7 @@ module ariane
.flush_tlb_o ( flush_tlb_ctrl_ex ),
.halt_csr_i ( halt_csr_ctrl ),
.halt_debug_i ( 1'b0 ),
.halt_debug_i ( halt_debug_ctrl ),
.halt_o ( halt_ctrl_commit ),
// control ports
.eret_i ( eret ),
@ -521,6 +540,32 @@ module ariane
.*
);
// ------------
// Debug
// ------------
debug_unit debug_unit_i (
.commit_instr_i ( commit_instr_id_commit ),
.commit_ack_i ( commit_ack ),
.ex_i ( ex_commit ),
.halt_o ( halt_debug_ctrl ),
.debug_pc_o ( pc_debug_pcgen ),
.debug_set_pc_o ( debug_set_pc_o ),
.debug_gpr_req_o ( gpr_req_debug_issue ),
.debug_gpr_addr_o ( gpr_addr_debug_issue ),
.debug_gpr_we_o ( gpr_we_debug_issue ),
.debug_gpr_wdata_o ( gpr_wdata_debug_issue ),
.debug_gpr_rdata_i ( gpr_rdata_debug_issue ),
.debug_csr_req_o ( csr_req_debug_csr ),
.debug_csr_addr_o ( csr_addr_debug_csr ),
.debug_csr_we_o ( csr_we_debug_csr ),
.debug_csr_wdata_o ( csr_wdata_debug_csr ),
.debug_csr_rdata_i ( csr_rdata_debug_csr ),
.*
);
// -------------------
// Instruction Tracer

7
src/pcgen_stage.sv
View file

@ -40,7 +40,10 @@ module pcgen (
input logic [63:0] epc_i, // exception PC which we need to return to
input logic eret_i, // return from exception
input logic [63:0] trap_vector_base_i, // base of trap vector
input exception ex_valid_i // exception is valid - from commit
input exception ex_valid_i, // exception is valid - from commit
// Debug
input logic [63:0] debug_pc_i, // PC from debug stage
input logic debug_set_pc_i // Set PC request from debug
);
logic [63:0] npc_n, npc_q;
@ -118,6 +121,8 @@ module pcgen (
// -------------------------------
// 2. Debug
// -------------------------------
if (debug_set_pc_i)
npc_n = debug_pc_i;
// -------------------------------
// 4. Exception