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Move timing statement outside of always_comb block (#2552)

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Fix following requirement:

The assertion included in the always_comb block apparently violates the requirements in [section 9.2.2.2.2 of the SystemVerilog standard](https://ieeexplore.ieee.org/document/10458102):

Statements in an always_comb shall not include those that block, have blocking timing or event
controls, or fork-join statements.
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Riccardo Tedeschi 2024-10-23 07:32:49 +02:00 • committed by GitHub
parent b4d000bb77
commit 53472eb026
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1 changed files with 2 additions and 1 deletions
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core/cache_subsystem/tag_cmp.sv
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@ -81,6 +81,8 @@ module tag_cmp #(
if (req_i[i]) break;
end
end
`ifndef SYNTHESIS
`ifndef VERILATOR
// assert that cache only hits on one way
@ -92,7 +94,6 @@ module tag_cmp #(
end
`endif
`endif
end
always_ff @(posedge clk_i or negedge rst_ni) begin
if (~rst_ni) begin