Add Verilator to CI

.gitlab-ci.yml

@@ -54,6 +54,15 @@ test_core_asm:
     - make run-asm-tests library=core_lib
     - vcover-10.6 report run-asm-tests.ucdb
 
+test_core_asm_verilator:
+  stage: test
+  before_script:
+    - git submodule update --init --recursive
+    - make build-tests
+    - make verilate
+  script:
+    - make run-asm-tests run-asm-tests-verilator
+
 # test with the randomized memory interfaces
 # test_core_asm_rand:
 #   stage: test

Makefile

@@ -138,6 +138,9 @@ run-asm-tests: build
 		-coverage -classdebug -do "coverage save -onexit $@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]"  \
 		$(library).$(test_top_level)_optimized;)
 
+run-asm-tests-verilator: verilate
+	$(foreach test, $(riscv-tests), obj_dir/Variane_wrapped $(riscv-test-dir)/$(test);)
+
 run-failed-tests: build
 	# make the tests
 	cd failedtests && make
@@ -174,7 +177,7 @@ build-tests:
 # User Verilator
 verilate:
 	verilator $(ariane_pkg) $(filter-out src/regfile.sv, $(wildcard src/*.sv)) src/util/behav_sram.sv src/axi_mem_if/axi2mem.sv tb/agents/axi_if/axi_if.sv \
-	-Wno-fatal -LDFLAGS "-lfesvr" -Wall --cc --trace \
+	--unroll-count 256 -Wno-fatal -LDFLAGS "-lfesvr" -Wall --cc --trace \
 	$(list_incdir) --top-module ariane_wrapped --exe tb/ariane_tb.cpp tb/simmem.cpp
 	cd obj_dir && make -j8 -f Variane_wrapped.mk
 

src/ariane_wrapped.sv

@@ -67,7 +67,7 @@ module ariane_wrapped #(
 
     localparam int unsigned AXI_NUMBYTES = AXI_DATA_WIDTH/8;
 
-    automatic longint unsigned tohost, fromhost;
+    longint unsigned tohost, fromhost;
 
     logic [63:0] instr_if_address;
     logic        instr_if_data_req;
@@ -123,8 +123,10 @@ module ariane_wrapped #(
     );
 
     // direct store interface
-    automatic logic [63:0] store_address;
     always_ff @(posedge clk_i or negedge rst_ni) begin
+
+        automatic logic [63:0] store_address;
+
         if (i_ariane.ex_stage_i.lsu_i.i_store_unit.data_req_o
           & i_ariane.ex_stage_i.lsu_i.i_store_unit.data_gnt_i
           & i_ariane.ex_stage_i.lsu_i.i_store_unit.data_we_o) begin

src/util/behav_sram.sv

@@ -10,7 +10,6 @@
 //
 // Date: 13.10.2017
 // Description: SRAM Behavioral Model
-//
 
 module sram #(
     int unsigned DATA_WIDTH = 64,
@@ -30,24 +29,18 @@ module sram #(
     logic [DATA_WIDTH-1:0] ram [NUM_WORDS-1:0];
     logic [ADDR_WIDTH-1:0] raddr_q;
 
-    logic [DATA_WIDTH-1:0] wdata;
-
     // 1. randomize array
     // 2. randomize output when no request is active
-
-    always @(posedge clk_i) begin
+    always_ff @(posedge clk_i) begin
         if (req_i) begin
             if (!we_i)
                 raddr_q <= addr_i;
             else
-                ram[addr_i] <= wdata;
+            for (int i = 0; i < DATA_WIDTH; i++)
+                if (be_i[i]) ram[addr_i][i] <= wdata_i[i];
         end
     end
 
     assign rdata_o = ram[raddr_q];
 
-    generate
-        for (genvar i = 0; i < DATA_WIDTH; i++)
-            assign wdata[i] = be_i[i] ? wdata_i[i] : wdata[i];
-    endgenerate
 endmodule

tb

@@ -1 +1 @@
-Subproject commit c3caf00d1d75045cb760b9f976ac78eb4120db16
+Subproject commit 8be95b0230c6b384bcc3241fb7c40bf23c0f2ed7