github-mirrors/cva6
1
0
Fork 0
mirror of https://github.com/openhwgroup/cva6.git synced 2025-04-22 05:07:21 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions 5

Merge pull request #2103 from ThalesSiliconSecurity/spike-yield-load-reservation

Browse source 
[SPIKE] sim.cc: do not yield load reservation on single core
This commit is contained in:
André Sintzoff 2023-08-07 08:37:43 +02:00 • committed by GitHub
commit 54747422ef
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
2 changed files with 16 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

14
vendor/patches/riscv/riscv-isa-sim/0005-yield-load-reservation.patch vendored Normal file
View file

@ -0,0 +1,14 @@
diff --git a/vendor/riscv/riscv-isa-sim/riscv/sim.cc b/vendor/riscv/riscv-isa-sim/riscv/sim.cc
index 8863a5f7..9179ee4e 100644
--- a/vendor/riscv/riscv-isa-sim/riscv/sim.cc
+++ b/vendor/riscv/riscv-isa-sim/riscv/sim.cc
@@ -257,7 +257,8 @@ void sim_t::step(size_t n)
if (current_step == INTERLEAVE)
{
current_step = 0;
- procs[current_proc]->get_mmu()->yield_load_reservation();
+ if (procs.size() > 1)
+ procs[current_proc]->get_mmu()->yield_load_reservation();
if (++current_proc == procs.size()) {
current_proc = 0;
if (clint) clint->increment(INTERLEAVE / INSNS_PER_RTC_TICK);

3
vendor/riscv/riscv-isa-sim/riscv/sim.cc vendored
View file

@ -257,7 +257,8 @@ void sim_t::step(size_t n)
if (current_step == INTERLEAVE)
{
current_step = 0;
procs[current_proc]->get_mmu()->yield_load_reservation();
if (procs.size() > 1)
procs[current_proc]->get_mmu()->yield_load_reservation();
if (++current_proc == procs.size()) {
current_proc = 0;
if (clint) clint->increment(INTERLEAVE / INSNS_PER_RTC_TICK);