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https://github.com/openhwgroup/cva6.git
synced 2025-04-23 05:37:16 -04:00
Add support for +max_cycle count
This commit is contained in:
Florian Zaruba
parent
fbd133510a
commit
569ab8c2d0
2 changed files with 105 additions and 86 deletions
6
Makefile
6
Makefile
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@ -56,6 +56,8 @@ riscv-tests = rv64ui-p-add rv64ui-p-addi rv64ui-p-slli rv64ui-p-addiw rv64ui-p-
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riscv-test = rv64ui-p-add
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# Search here for include files (e.g.: non-standalone components)
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incdir = ./includes
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# Maximum amount of cycles for a successful simulation run
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max_cycles = 10000000
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# Test case to run
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test_case = core_test
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# QuestaSim Version
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@ -113,10 +115,10 @@ sim: build
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vsim${questa_version} -lib ${library} ${top_level}_optimized +UVM_TESTNAME=${test_case} +BASEDIR=$(riscv-test-dir) +ASMTEST=$(riscv-test) -coverage -classdebug -do "do tb/wave/wave_core.do"
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simc: build
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vsim${questa_version} -c -lib ${library} ${top_level}_optimized +signature=output/test.rtlsim.sig +UVM_TESTNAME=${test_case} +BASEDIR=$(riscv-test-dir) +ASMTEST=$(riscv-test) -coverage -classdebug -do "do tb/wave/wave_core.do"
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vsim${questa_version} -c -lib ${library} ${top_level}_optimized +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} +BASEDIR=$(riscv-test-dir) +ASMTEST=$(riscv-test) -coverage -classdebug -do "do tb/wave/wave_core.do"
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run-asm-tests: build
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$(foreach test, $(riscv-tests), vsim$(questa_version) +BASEDIR=$(riscv-test-dir) +UVM_TESTNAME=$(test_case) +ASMTEST=$(test) +uvm_set_action="*,_ALL_,UVM_ERROR,UVM_DISPLAY|UVM_STOP" -c -coverage -classdebug -do "coverage save -onexit $@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" $(library).$(test_top_level)_optimized;)
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$(foreach test, $(riscv-tests), vsim$(questa_version) +BASEDIR=$(riscv-test-dir) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) +ASMTEST=$(test) +uvm_set_action="*,_ALL_,UVM_ERROR,UVM_DISPLAY|UVM_STOP" -c -coverage -classdebug -do "coverage save -onexit $@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]" $(library).$(test_top_level)_optimized;)
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# Run the specified test case
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$(tests): build
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185
tb/core_tb.sv
185
tb/core_tb.sv
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@ -31,10 +31,15 @@ module core_tb;
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import "DPI-C" function longint unsigned get_section_size(string symb);
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import "DPI-C" function longint unsigned get_symbol_address(string symb);
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static uvm_cmdline_processor uvcl = uvm_cmdline_processor::get_inst();
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logic clk_i;
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logic rst_ni;
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logic rtc_i;
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longint unsigned cycles;
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longint unsigned max_cycles;
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debug_if debug_if();
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core_if core_if (clk_i);
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dcache_if dcache_if (clk_i);
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@ -72,76 +77,76 @@ module core_tb;
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assign dcache_if.data_rdata = data_if_data_rdata_o;
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core_mem core_mem_i (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.instr_if_address_i ( instr_if_address ),
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.instr_if_data_req_i ( instr_if_data_req ),
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.instr_if_data_be_i ( instr_if_data_be ),
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.instr_if_data_gnt_o ( instr_if_data_gnt ),
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.instr_if_data_rvalid_o ( instr_if_data_rvalid ),
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.instr_if_data_rdata_o ( instr_if_data_rdata ),
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.instr_if_address_i ( instr_if_address ),
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.instr_if_data_req_i ( instr_if_data_req ),
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.instr_if_data_be_i ( instr_if_data_be ),
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.instr_if_data_gnt_o ( instr_if_data_gnt ),
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.instr_if_data_rvalid_o ( instr_if_data_rvalid ),
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.instr_if_data_rdata_o ( instr_if_data_rdata ),
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.data_if_address_index_i ( data_if_address_index_i ),
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.data_if_address_tag_i ( data_if_address_tag_i ),
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.data_if_data_wdata_i ( data_if_data_wdata_i ),
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.data_if_data_req_i ( data_if_data_req_i ),
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.data_if_data_we_i ( data_if_data_we_i ),
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.data_if_data_be_i ( data_if_data_be_i ),
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.data_if_kill_req_i ( data_if_kill_req_i ),
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.data_if_tag_valid_i ( data_if_tag_valid_i ),
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.data_if_data_gnt_o ( data_if_data_gnt_o ),
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.data_if_data_rvalid_o ( data_if_data_rvalid_o ),
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.data_if_data_rdata_o ( data_if_data_rdata_o )
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.data_if_address_index_i ( data_if_address_index_i ),
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.data_if_address_tag_i ( data_if_address_tag_i ),
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.data_if_data_wdata_i ( data_if_data_wdata_i ),
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.data_if_data_req_i ( data_if_data_req_i ),
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.data_if_data_we_i ( data_if_data_we_i ),
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.data_if_data_be_i ( data_if_data_be_i ),
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.data_if_kill_req_i ( data_if_kill_req_i ),
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.data_if_tag_valid_i ( data_if_tag_valid_i ),
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.data_if_data_gnt_o ( data_if_data_gnt_o ),
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.data_if_data_rvalid_o ( data_if_data_rvalid_o ),
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.data_if_data_rdata_o ( data_if_data_rdata_o )
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);
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ariane dut (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.rtc_i ( rtc_i ),
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.clock_en_i ( core_if.clock_en ),
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.test_en_i ( core_if.test_en ),
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.fetch_enable_i ( core_if.fetch_enable ),
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.core_busy_o ( core_if.core_busy ),
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.ext_perf_counters_i ( ),
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.boot_addr_i ( core_if.boot_addr ),
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.core_id_i ( core_if.core_id ),
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.cluster_id_i ( core_if.cluster_id ),
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.rtc_i ( rtc_i ),
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.clock_en_i ( core_if.clock_en ),
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.test_en_i ( core_if.test_en ),
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.fetch_enable_i ( core_if.fetch_enable ),
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.core_busy_o ( core_if.core_busy ),
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.ext_perf_counters_i ( ),
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.boot_addr_i ( core_if.boot_addr ),
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.core_id_i ( core_if.core_id ),
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.cluster_id_i ( core_if.cluster_id ),
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.instr_if_address_o ( instr_if_address ),
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.instr_if_data_req_o ( instr_if_data_req ),
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.instr_if_data_be_o ( instr_if_data_be ),
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.instr_if_data_gnt_i ( instr_if_data_gnt ),
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.instr_if_data_rvalid_i ( instr_if_data_rvalid ),
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.instr_if_data_rdata_i ( instr_if_data_rdata ),
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.instr_if_address_o ( instr_if_address ),
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.instr_if_data_req_o ( instr_if_data_req ),
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.instr_if_data_be_o ( instr_if_data_be ),
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.instr_if_data_gnt_i ( instr_if_data_gnt ),
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.instr_if_data_rvalid_i ( instr_if_data_rvalid ),
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.instr_if_data_rdata_i ( instr_if_data_rdata ),
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.data_if_address_index_o ( data_if_address_index_i ),
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.data_if_address_tag_o ( data_if_address_tag_i ),
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.data_if_data_wdata_o ( data_if_data_wdata_i ),
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.data_if_data_req_o ( data_if_data_req_i ),
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.data_if_data_we_o ( data_if_data_we_i ),
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.data_if_data_be_o ( data_if_data_be_i ),
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.data_if_kill_req_o ( data_if_kill_req_i ),
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.data_if_tag_valid_o ( data_if_tag_valid_i ),
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.data_if_data_gnt_i ( data_if_data_gnt_o ),
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.data_if_data_rvalid_i ( data_if_data_rvalid_o ),
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.data_if_data_rdata_i ( data_if_data_rdata_o ),
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.data_if_address_index_o ( data_if_address_index_i ),
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.data_if_address_tag_o ( data_if_address_tag_i ),
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.data_if_data_wdata_o ( data_if_data_wdata_i ),
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.data_if_data_req_o ( data_if_data_req_i ),
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.data_if_data_we_o ( data_if_data_we_i ),
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.data_if_data_be_o ( data_if_data_be_i ),
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.data_if_kill_req_o ( data_if_kill_req_i ),
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.data_if_tag_valid_o ( data_if_tag_valid_i ),
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.data_if_data_gnt_i ( data_if_data_gnt_o ),
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.data_if_data_rvalid_i ( data_if_data_rvalid_o ),
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.data_if_data_rdata_i ( data_if_data_rdata_o ),
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.irq_i ( {core_if.irq, core_if.irq} ),
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.irq_id_i ( core_if.irq_id ),
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.irq_ack_o ( core_if.irq_ack ),
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.irq_sec_i ( core_if.irq_sec ),
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.sec_lvl_o ( core_if.sec_lvl ),
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.irq_i ( {core_if.irq, core_if.irq} ),
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.irq_id_i ( core_if.irq_id ),
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.irq_ack_o ( core_if.irq_ack ),
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.irq_sec_i ( core_if.irq_sec ),
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.sec_lvl_o ( core_if.sec_lvl ),
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.debug_req_i ( ),
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.debug_gnt_o ( ),
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.debug_rvalid_o ( ),
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.debug_addr_i ( ),
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.debug_we_i ( ),
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.debug_wdata_i ( ),
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.debug_rdata_o ( ),
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.debug_halted_o ( ),
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.debug_halt_i ( ),
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.debug_resume_i ( )
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.debug_req_i ( ),
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.debug_gnt_o ( ),
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.debug_rvalid_o ( ),
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.debug_addr_i ( ),
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.debug_we_i ( ),
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.debug_wdata_i ( ),
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.debug_rdata_o ( ),
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.debug_halted_o ( ),
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.debug_halt_i ( ),
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.debug_resume_i ( )
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);
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// Clock process
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@ -151,8 +156,15 @@ module core_tb;
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repeat(8)
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#10ns clk_i = ~clk_i;
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rst_ni = 1'b1;
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forever
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#10ns clk_i = ~clk_i;
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forever begin
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#10ns clk_i = 1'b1;
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#10ns clk_i = 1'b0;
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if (cycles > max_cycles)
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$fatal(1, "Simulation reached maximum cycle count of %d", max_cycles);
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cycles++;
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end
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end
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// Real Time Clock
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initial begin
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@ -162,13 +174,10 @@ module core_tb;
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end
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task preload_memories();
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static uvm_cmdline_processor uvcl = uvm_cmdline_processor::get_inst();
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string plus_args [$];
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longint unsigned address;
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longint unsigned bss_address;
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longint unsigned bss_size;
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longint unsigned begin_signature_address;
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string file;
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string file_name;
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@ -176,6 +185,7 @@ module core_tb;
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string test;
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// offset the temporary RAM
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logic [7:0] rmem [`DRAM_BASE:`DRAM_BASE + 32768];
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// get the file name from a command line plus arg
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void'(uvcl.get_arg_value("+BASEDIR=", base_dir));
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void'(uvcl.get_arg_value("+ASMTEST=", file_name));
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@ -185,8 +195,7 @@ module core_tb;
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$display("Pre-loading memory from file: %s\n", file);
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// read elf file (DPI call)
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void'(read_elf(file));
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// we are interested in the .tohost ELF symbol in-order to observe end of test signals
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address = get_section_address(".tohost");
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// get the objdump verilog file to load our memorys
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$readmemh({file, ".v"}, rmem);
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// copy bitwise from verilog file
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@ -197,32 +206,40 @@ module core_tb;
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// initialize .bss
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bss_address = get_section_address(".bss");
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bss_size = get_section_size(".bss");
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begin_signature_address = get_symbol_address("begin_signature");
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$display("begin_signature: %x, end_signature %x, .bss address: %x, .bss size: %x, .tohost address: %x",get_symbol_address("end_signature"), begin_signature_address, bss_address, bss_size, address);
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// the section should be aligned on a double word boundary
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for (int i = 0; i < bss_size/8; i++) begin
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core_mem_i.ram_i.mem[((bss_address - `DRAM_BASE) >> 3) + i] = 64'b0;
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end
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// pass tohost address to UVM resource DB
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uvm_config_db #(longint unsigned)::set(null, "uvm_test_top.m_env.m_eoc", "tohost", address);
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uvm_config_db #(longint unsigned)::set(null, "uvm_test_top.m_env.m_eoc", "begin_signature", ((begin_signature_address -`DRAM_BASE) >> 3));
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endtask : preload_memories
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program testbench (core_if core_if, dcache_if dcache_if);
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initial begin
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uvm_config_db #(virtual core_if)::set(null, "uvm_test_top", "core_if", core_if);
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uvm_config_db #(virtual dcache_if )::set(null, "uvm_test_top", "dcache_if", dcache_if);
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// print the topology
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// uvm_top.enable_print_topology = 1;
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// Start UVM test
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run_test();
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end
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longint unsigned begin_signature_address;
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longint unsigned tohost_address;
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string max_cycle_string;
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initial begin
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preload_memories();
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uvm_config_db #(virtual core_if)::set(null, "uvm_test_top", "core_if", core_if);
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uvm_config_db #(virtual dcache_if )::set(null, "uvm_test_top", "dcache_if", dcache_if);
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// we are interested in the .tohost ELF symbol in-order to observe end of test signals
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tohost_address = get_section_address(".tohost");
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begin_signature_address = get_symbol_address("begin_signature");
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// pass tohost address to UVM resource DB
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uvm_config_db #(longint unsigned)::set(null, "uvm_test_top.m_env.m_eoc", "tohost", tohost_address);
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uvm_config_db #(longint unsigned)::set(null, "uvm_test_top.m_env.m_eoc", "begin_signature", ((begin_signature_address -`DRAM_BASE) >> 3));
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// print the topology
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// uvm_top.enable_print_topology = 1;
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// get the maximum cycle count the simulation is allowed to run
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if (uvcl.get_arg_value("+max-cycles=", max_cycle_string) == 0) begin
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max_cycles = {64{1'b1}};
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end else begin
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max_cycles = max_cycle_string.atoi();
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end
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// Start UVM test
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run_test();
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end
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endprogram
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