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https://github.com/openhwgroup/cva6.git
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[std_cache_subsystem] Add fourth dcache request port
This commit is contained in:
Domenic Wüthrich
parent
aad93781e5
commit
570c52992f
3 changed files with 58 additions and 53 deletions
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@ -18,7 +18,7 @@
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module miss_handler import ariane_pkg::*; import std_cache_pkg::*; #(
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parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
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parameter int unsigned NR_PORTS = 3,
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parameter int unsigned NR_PORTS = 4,
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parameter type axi_req_t = logic,
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parameter type axi_rsp_t = logic
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)(
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@ -524,7 +524,7 @@ module miss_handler import ariane_pkg::*; import std_cache_pkg::*; #(
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bypass_ports_req[id].req = miss_req_valid[id] & miss_req_bypass[id];
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bypass_ports_req[id].reqtype = ariane_pkg::SINGLE_REQ;
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bypass_ports_req[id].amo = AMO_NONE;
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bypass_ports_req[id].id = {2'b10, id};
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bypass_ports_req[id].id = 4'b1000 | 4'(id);
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bypass_ports_req[id].addr = miss_req_addr[id];
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bypass_ports_req[id].wdata = miss_req_wdata[id];
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bypass_ports_req[id].we = miss_req_we[id];
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@ -619,7 +619,7 @@ module miss_handler import ariane_pkg::*; import std_cache_pkg::*; #(
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.wdata_i ( req_fsm_miss_wdata ),
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.be_i ( req_fsm_miss_be ),
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.size_i ( req_fsm_miss_size ),
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.id_i ( {{CVA6Cfg.AxiIdWidth-4{1'b0}}, 4'b1100} ),
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.id_i ( {{CVA6Cfg.AxiIdWidth-4{1'b0}}, 4'b0111} ),
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.valid_o ( valid_miss_fsm ),
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.rdata_o ( data_miss_fsm ),
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.id_o ( ),
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@ -18,6 +18,7 @@
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module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #(
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parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
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parameter ariane_cfg_t ArianeCfg = ArianeDefaultConfig, // contains cacheable regions
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parameter int unsigned NumPorts = 4,
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parameter type axi_ar_chan_t = logic,
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parameter type axi_aw_chan_t = logic,
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parameter type axi_w_chan_t = logic,
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@ -48,8 +49,8 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #(
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output logic dcache_miss_o, // we missed on a ld/st
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output logic wbuffer_empty_o, // statically set to 1, as there is no wbuffer in this cache system
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// Request ports
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input dcache_req_i_t [2:0] dcache_req_ports_i, // to/from LSU
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output dcache_req_o_t [2:0] dcache_req_ports_o, // to/from LSU
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input dcache_req_i_t [NumPorts-1:0] dcache_req_ports_i, // to/from LSU
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output dcache_req_o_t [NumPorts-1:0] dcache_req_ports_o, // to/from LSU
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// memory side
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output axi_req_t axi_req_o,
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input axi_rsp_t axi_resp_i
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@ -87,10 +88,12 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #(
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// decreasing priority
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// Port 0: PTW
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// Port 1: Load Unit
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// Port 2: Store Unit
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// Port 2: Accelerator
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// Port 3: Store Unit
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std_nbdcache #(
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.CVA6Cfg ( CVA6Cfg ),
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.ArianeCfg ( ArianeCfg ),
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.NumPorts ( NumPorts ),
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.axi_req_t ( axi_req_t ),
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.axi_rsp_t ( axi_rsp_t )
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) i_nbdcache (
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@ -151,10 +154,10 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #(
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// to forward the correct write data.
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always_comb begin
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w_select = 0;
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unique case (axi_req_o.aw.id)
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4'b1100: w_select = 2; // dcache
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4'b1000, 4'b1001, 4'b1010, 4'b1011: w_select = 1; // bypass
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default: w_select = 0; // icache
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unique casez (axi_req_o.aw.id)
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4'b0111: w_select = 2; // dcache
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4'b1???: w_select = 1; // bypass
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default: w_select = 0; // icache
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endcase
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end
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@ -199,9 +202,9 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #(
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);
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// Route responses based on ID
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// 0000 -> I$
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// 10[00|10|01|11] -> Bypass
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// 1100 -> D$
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// 0000 -> I$
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// 0111 -> D$
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// 1??? -> Bypass
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// R Channel
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assign axi_resp_icache.r = axi_resp_i.r;
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assign axi_resp_bypass.r = axi_resp_i.r;
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@ -211,11 +214,11 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #(
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always_comb begin
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r_select = 0;
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unique case (axi_resp_i.r.id)
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4'b1100: r_select = 0; // dcache
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4'b1000, 4'b1001, 4'b1010, 4'b1011: r_select = 1; // bypass
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4'b0000: r_select = 2; // icache
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default: r_select = 0;
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unique casez (axi_resp_i.r.id)
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4'b0111: r_select = 0; // dcache
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4'b1???: r_select = 1; // bypass
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4'b0000: r_select = 2; // icache
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default: r_select = 0;
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endcase
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end
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@ -238,11 +241,11 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #(
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always_comb begin
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b_select = 0;
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unique case (axi_resp_i.b.id)
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4'b1100: b_select = 0; // dcache
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4'b1000, 4'b1001, 4'b1010, 4'b1011: b_select = 1; // bypass
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4'b0000: b_select = 2; // icache
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default: b_select = 0;
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unique casez (axi_resp_i.b.id)
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4'b0111: b_select = 0; // dcache
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4'b1???: b_select = 1; // bypass
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4'b0000: b_select = 2; // icache
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default: b_select = 0;
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endcase
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end
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@ -269,11 +272,11 @@ module std_cache_subsystem import ariane_pkg::*; import std_cache_pkg::*; #(
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icache_dreq_o.vaddr, icache_dreq_o.data);
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a_invalid_write_data: assert property (
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@(posedge clk_i) disable iff (~rst_ni) dcache_req_ports_i[2].data_req |-> |dcache_req_ports_i[2].data_be |-> (|dcache_req_ports_i[2].data_wdata) !== 1'hX)
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@(posedge clk_i) disable iff (~rst_ni) dcache_req_ports_i[NumPorts-1].data_req |-> |dcache_req_ports_i[NumPorts-1].data_be |-> (|dcache_req_ports_i[NumPorts-1].data_wdata) !== 1'hX)
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else $warning(1,"[l1 dcache] writing invalid data: paddr=%016X, be=%02X, data=%016X",
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{dcache_req_ports_i[2].address_tag, dcache_req_ports_i[2].address_index}, dcache_req_ports_i[2].data_be, dcache_req_ports_i[2].data_wdata);
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{dcache_req_ports_i[NumPorts-1].address_tag, dcache_req_ports_i[NumPorts-1].address_index}, dcache_req_ports_i[NumPorts-1].data_be, dcache_req_ports_i[NumPorts-1].data_wdata);
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generate
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for(genvar j=0; j<2; j++) begin
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for(genvar j=0; j<NumPorts-1; j++) begin
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a_invalid_read_data: assert property (
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@(posedge clk_i) disable iff (~rst_ni) dcache_req_ports_o[j].data_rvalid |-> (|dcache_req_ports_o[j].data_rdata) !== 1'hX)
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else $warning(1,"[l1 dcache] reading invalid data on port %01d: data=%016X",
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@ -16,6 +16,7 @@
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module std_nbdcache import std_cache_pkg::*; import ariane_pkg::*; #(
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parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
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parameter ariane_cfg_t ArianeCfg = ArianeDefaultConfig, // contains cacheable regions
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parameter int unsigned NumPorts = 4,
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parameter type axi_req_t = logic,
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parameter type axi_rsp_t = logic
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)(
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@ -30,8 +31,8 @@ module std_nbdcache import std_cache_pkg::*; import ariane_pkg::*; #(
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input amo_req_t amo_req_i,
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output amo_resp_t amo_resp_o,
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// Request ports
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input dcache_req_i_t [2:0] req_ports_i, // request ports
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output dcache_req_o_t [2:0] req_ports_o, // request ports
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input dcache_req_i_t [NumPorts-1:0] req_ports_i, // request ports
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output dcache_req_o_t [NumPorts-1:0] req_ports_o, // request ports
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// Cache AXI refill port
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output axi_req_t axi_data_o,
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input axi_rsp_t axi_data_i,
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@ -47,34 +48,35 @@ import std_cache_pkg::*;
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// 1. Miss handler
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// 2. PTW
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// 3. Load Unit
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// 4. Store unit
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logic [3:0][DCACHE_SET_ASSOC-1:0] req;
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logic [3:0][DCACHE_INDEX_WIDTH-1:0]addr;
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logic [3:0] gnt;
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cache_line_t [DCACHE_SET_ASSOC-1:0] rdata;
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logic [3:0][DCACHE_TAG_WIDTH-1:0] tag;
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// 4. Accelerator
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// 5. Store unit
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logic [NumPorts:0][DCACHE_SET_ASSOC-1:0] req;
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logic [NumPorts:0][DCACHE_INDEX_WIDTH-1:0]addr;
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logic [NumPorts:0] gnt;
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cache_line_t [DCACHE_SET_ASSOC-1:0] rdata;
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logic [NumPorts:0][DCACHE_TAG_WIDTH-1:0] tag;
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cache_line_t [3:0] wdata;
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logic [3:0] we;
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cl_be_t [3:0] be;
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logic [DCACHE_SET_ASSOC-1:0] hit_way;
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cache_line_t [NumPorts:0] wdata;
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logic [NumPorts:0] we;
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cl_be_t [NumPorts:0] be;
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logic [DCACHE_SET_ASSOC-1:0] hit_way;
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// -------------------------------
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// Controller <-> Miss unit
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// -------------------------------
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logic [2:0] busy;
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logic [2:0][55:0] mshr_addr;
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logic [2:0] mshr_addr_matches;
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logic [2:0] mshr_index_matches;
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logic [63:0] critical_word;
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logic critical_word_valid;
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logic [NumPorts-1:0] busy;
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logic [NumPorts-1:0][55:0] mshr_addr;
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logic [NumPorts-1:0] mshr_addr_matches;
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logic [NumPorts-1:0] mshr_index_matches;
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logic [63:0] critical_word;
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logic critical_word_valid;
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logic [2:0][$bits(miss_req_t)-1:0] miss_req;
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logic [2:0] miss_gnt;
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logic [2:0] active_serving;
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logic [NumPorts-1:0][$bits(miss_req_t)-1:0] miss_req;
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logic [NumPorts-1:0] miss_gnt;
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logic [NumPorts-1:0] active_serving;
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logic [2:0] bypass_gnt;
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logic [2:0] bypass_valid;
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logic [2:0][63:0] bypass_data;
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logic [NumPorts-1:0] bypass_gnt;
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logic [NumPorts-1:0] bypass_valid;
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logic [NumPorts-1:0][63:0] bypass_data;
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// -------------------------------
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// Arbiter <-> Datram,
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// -------------------------------
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@ -89,7 +91,7 @@ import std_cache_pkg::*;
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// Cache Controller
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// ------------------
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generate
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for (genvar i = 0; i < 3; i++) begin : master_ports
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for (genvar i = 0; i < NumPorts; i++) begin : master_ports
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cache_ctrl #(
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.CVA6Cfg ( CVA6Cfg ),
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.ArianeCfg ( ArianeCfg )
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@ -132,7 +134,7 @@ import std_cache_pkg::*;
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// ------------------
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miss_handler #(
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.CVA6Cfg ( CVA6Cfg ),
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.NR_PORTS ( 3 ),
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.NR_PORTS ( NumPorts ),
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.axi_req_t ( axi_req_t ),
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.axi_rsp_t ( axi_rsp_t )
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) i_miss_handler (
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@ -243,7 +245,7 @@ import std_cache_pkg::*;
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// ------------------------------------------------
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tag_cmp #(
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.CVA6Cfg ( CVA6Cfg ),
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.NR_PORTS ( 4 ),
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.NR_PORTS ( NumPorts+1 ),
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.ADDR_WIDTH ( DCACHE_INDEX_WIDTH ),
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.DCACHE_SET_ASSOC ( DCACHE_SET_ASSOC )
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) i_tag_cmp (
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