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Add [s|m]counteren as they are mandatory

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This commit is contained in:
Florian Zaruba 2017-07-15 10:14:31 +02:00
parent 45866aaaca
commit 58047f581b
3 changed files with 34 additions and 26 deletions
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54
include/ariane_pkg.svh
View file

@ -255,33 +255,35 @@ package ariane_pkg;
// CSRs
// -----
typedef enum logic [11:0] {
CSR_SSTATUS = 12'h100,
CSR_SIE = 12'h104,
CSR_STVEC = 12'h105,
CSR_SSCRATCH = 12'h140,
CSR_SEPC = 12'h141,
CSR_SCAUSE = 12'h142,
CSR_STVAL = 12'h143,
CSR_SIP = 12'h144,
CSR_SATP = 12'h180,
CSR_SSTATUS = 12'h100,
CSR_SIE = 12'h104,
CSR_STVEC = 12'h105,
CSR_SCOUNTEREN = 12'h106,
CSR_SSCRATCH = 12'h140,
CSR_SEPC = 12'h141,
CSR_SCAUSE = 12'h142,
CSR_STVAL = 12'h143,
CSR_SIP = 12'h144,
CSR_SATP = 12'h180,
CSR_MSTATUS = 12'h300,
CSR_MISA = 12'h301,
CSR_MEDELEG = 12'h302,
CSR_MIDELEG = 12'h303,
CSR_MIE = 12'h304,
CSR_MTVEC = 12'h305,
CSR_MSCRATCH = 12'h340,
CSR_MEPC = 12'h341,
CSR_MCAUSE = 12'h342,
CSR_MTVAL = 12'h343,
CSR_MIP = 12'h344,
CSR_MVENDORID = 12'hF11,
CSR_MARCHID = 12'hF12,
CSR_MIMPID = 12'hF13,
CSR_MHARTID = 12'hF14,
CSR_MCYCLE = 12'hB00,
CSR_MINSTRET = 12'hB02,
CSR_MSTATUS = 12'h300,
CSR_MISA = 12'h301,
CSR_MEDELEG = 12'h302,
CSR_MIDELEG = 12'h303,
CSR_MIE = 12'h304,
CSR_MTVEC = 12'h305,
CSR_MCOUNTEREN = 12'h306,
CSR_MSCRATCH = 12'h340,
CSR_MEPC = 12'h341,
CSR_MCAUSE = 12'h342,
CSR_MTVAL = 12'h343,
CSR_MIP = 12'h344,
CSR_MVENDORID = 12'hF11,
CSR_MARCHID = 12'hF12,
CSR_MIMPID = 12'hF13,
CSR_MHARTID = 12'hF14,
CSR_MCYCLE = 12'hB00,
CSR_MINSTRET = 12'hB02,
// Counters and Timers
CSR_CYCLE = 12'hC00,
CSR_TIME = 12'hC01,

4
src/csr_regfile.sv
View file

@ -160,6 +160,7 @@ module csr_regfile #(
CSR_SIE: csr_rdata = mie_q & mideleg_q;
CSR_SIP: csr_rdata = mip_q & mideleg_q;
CSR_STVEC: csr_rdata = stvec_q;
CSR_SCOUNTEREN: csr_rdata = 64'b0; // not implemented
CSR_SSCRATCH: csr_rdata = sscratch_q;
CSR_SEPC: csr_rdata = sepc_q;
CSR_SCAUSE: csr_rdata = scause_q;
@ -179,6 +180,7 @@ module csr_regfile #(
CSR_MIP: csr_rdata = mip_q;
CSR_MIE: csr_rdata = mie_q;
CSR_MTVEC: csr_rdata = mtvec_q;
CSR_MCOUNTEREN: csr_rdata = 64'b0; // not implemented
CSR_MSCRATCH: csr_rdata = mscratch_q;
CSR_MEPC: csr_rdata = mepc_q;
CSR_MCAUSE: csr_rdata = mcause_q;
@ -239,6 +241,7 @@ module csr_regfile #(
// if the corresponding bit in mideleg is set
CSR_SIE: mie_n = csr_wdata & 64'hBBB & mideleg_q; // we only support supervisor and m-mode interrupts
CSR_SIP: mip_n = csr_wdata & 64'h33 & mideleg_q; // only SSIP, STIP are write-able
CSR_SCOUNTEREN:;
CSR_STVEC: stvec_n = {csr_wdata[63:2], 1'b0, csr_wdata[0]};
CSR_SSCRATCH: sscratch_n = csr_wdata;
CSR_SEPC: sepc_n = {csr_wdata[63:1], 1'b0};
@ -293,6 +296,7 @@ module csr_regfile #(
if (csr_wdata[0])
mtvec_n = {csr_wdata[63:8], 7'b0, csr_wdata[0]};
end
CSR_MCOUNTEREN:;
CSR_MSCRATCH: mscratch_n = csr_wdata;
CSR_MEPC: mepc_n = {csr_wdata[63:1], 1'b0};
CSR_MCAUSE: mcause_n = csr_wdata;

2
src/util/instruction_trace_item.svh
View file

@ -64,6 +64,7 @@ class instruction_trace_item;
CSR_SSTATUS: return "sstatus";
CSR_SIE: return "sie";
CSR_STVEC: return "stvec";
CSR_SCOUNTEREN: return "scounteren";
CSR_SSCRATCH: return "sscratch";
CSR_SEPC: return "sepc";
CSR_SCAUSE: return "scause";
@ -77,6 +78,7 @@ class instruction_trace_item;
CSR_MIDELEG: return "mideleg";
CSR_MIE: return "mie";
CSR_MTVEC: return "mtvec";
CSR_MCOUNTEREN: return "mcounteren";
CSR_MSCRATCH: return "mscratch";
CSR_MEPC: return "mepc";
CSR_MCAUSE: return "mcause";