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Remove DROMAJO (#1204)

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Signed-off-by: Jean-Roch Coulon <jean-roch.coulon@thalesgroup.com>
This commit is contained in:
JeanRochCoulon 2023-04-24 23:05:53 +02:00 • committed by GitHub
parent a3e6521f97
commit 59a1df031c
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GPG key ID: 4AEE18F83AFDEB23
13 changed files with 16 additions and 525 deletions
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3
.gitmodules vendored
View file

@ -31,9 +31,6 @@
[submodule "corev_apu/fpga/src/apb_timer"]
path = corev_apu/fpga/src/apb_timer
url = https://github.com/pulp-platform/apb_timer.git
[submodule "corev_apu/tb/dromajo"]
path = corev_apu/tb/dromajo
url = https://github.com/kabylkas/dromajo.git
[submodule "corev_apu/tb/common_verification"]
path = corev_apu/tb/common_verification
url = https://github.com/pulp-platform/common_verification.git

74
Makefile
View file

@ -113,18 +113,12 @@ ifndef spike-tandem
dpi := $(filter-out ${dpi-library}/spike.o ${dpi-library}/sim_spike.o, $(dpi))
endif
# filter dromajo stuff if dromajo is not activated
ifndef DROMAJO
dpi := $(filter-out ${dpi-library}/dromajo_cosim_dpi.o, $(dpi))
endif
dpi_hdr := $(wildcard corev_apu/tb/dpi/*.h)
dpi_hdr := $(addprefix $(root-dir), $(dpi_hdr))
CFLAGS += -I$(QUESTASIM_HOME)/include \
-I$(VCS_HOME)/include \
-I$(RISCV)/include \
-I$(SPIKE_ROOT)/include \
$(if $(DROMAJO), -I../corev_apu/tb/dromajo/src,) \
-std=c++11 -I../corev_apu/tb/dpi -O3
ifdef XCELIUM_HOME
@ -548,82 +542,22 @@ verilate_command := $(verilator) verilator_config.vlt
-Wno-BLKANDNBLK \
-Wno-style \
$(if ($(PRELOAD)!=""), -DPRELOAD=1,) \
$(if $(DROMAJO), -DDROMAJO=1,) \
$(if $(PROFILE),--stats --stats-vars --profile-cfuncs,) \
$(if $(DEBUG), --trace-structs,) \
$(if $(TRACE_COMPACT), --trace-fst $(VERILATOR_ROOT)/include/verilated_fst_c.cpp) \
$(if $(TRACE_FAST), --trace $(VERILATOR_ROOT)/include/verilated_vcd_c.cpp,) \
-LDFLAGS "-L$(RISCV)/lib -L$(SPIKE_ROOT)/lib -Wl,-rpath,$(RISCV)/lib -Wl,-rpath,$(SPIKE_ROOT)/lib -lfesvr$(if $(PROFILE), -g -pg,) $(if $(DROMAJO), -L../corev_apu/tb/dromajo/src -ldromajo_cosim,) -lpthread $(if $(TRACE_COMPACT), -lz,)" \
-CFLAGS "$(CFLAGS)$(if $(PROFILE), -g -pg,) $(if $(DROMAJO), -DDROMAJO=1,) -DVL_DEBUG" \
-LDFLAGS "-L$(RISCV)/lib -L$(SPIKE_ROOT)/lib -Wl,-rpath,$(RISCV)/lib -Wl,-rpath,$(SPIKE_ROOT)/lib -lfesvr$(if $(PROFILE), -g -pg,) -lpthread $(if $(TRACE_COMPACT), -lz,)" \
-CFLAGS "$(CFLAGS)$(if $(PROFILE), -g -pg,) -DVL_DEBUG" \
--cc --vpi \
$(list_incdir) --top-module ariane_testharness \
--threads-dpi none \
--Mdir $(ver-library) -O3 \
--exe corev_apu/tb/ariane_tb.cpp corev_apu/tb/dpi/SimDTM.cc corev_apu/tb/dpi/SimJTAG.cc \
corev_apu/tb/dpi/remote_bitbang.cc corev_apu/tb/dpi/msim_helper.cc $(if $(DROMAJO), corev_apu/tb/dpi/dromajo_cosim_dpi.cc,)
dromajo:
cd ./tb/dromajo/src && make
run-dromajo-verilator:
$(if $(BIN), $(MAKE) checkpoint_dromajo, $(error "Please provide absolute path to the binary. Usage: make run_dromajo BIN=/absolute/path/to/binary"))
checkpoint_dromajo:
cd ./tb/dromajo/run/checkpoints/ && \
rm -rf $(notdir $(BIN)) && mkdir $(notdir $(BIN)) && cd $(notdir $(BIN)) && \
cp $(BIN) . && \
echo -e "\
{\n\
\"version\":1,\n\
\"machine\":\"riscv64\",\n\
\"memory_size\":256,\n\
\"bios\":\"$(shell pwd)/tb/dromajo/run/checkpoints/$(notdir $(BIN))/$(notdir $(BIN))\",\n\
\"memory_base_addr\":0x80000000,\n\
\"missing_csrs\": [0x323, 0x324, 0x325, 0x326, //mhpmevent csrs\n\
0x327, 0x328, 0x329, 0x32a,\n\
0x32b, 0x32c, 0x32d, 0x32e,\n\
0x32f, 0x330, 0x331, 0x332,\n\
0x333, 0x334, 0x335, 0x336,\n\
0x337, 0x338, 0x339, 0x33a,\n\
0x33b, 0x33c, 0x33d, 0x33e,\n\
0x33f,\n\
0x3a0, 0x3a1, 0x3a2, 0x3a3, //pmp csrs\n\
0x3b0, 0x3b1, 0x3b2, 0x3b3,\n\
0x3b4, 0x3b5, 0x3b6, 0x3b7,\n\
0x3b8, 0x3b9, 0x3ba, 0x3bb,\n\
0x3bc, 0x3bd, 0x3be, 0x3bf,\n\
0x320], //mcountinhibit\n\
\"maxinsns\": 100,\n\
\"clint_base_addr\": 0x02000000,\n\
\"clint_size\": 0xC0000,\n\
\"plic_base_addr\": 0x0C000000,\n\
\"plic_size\": 0x3FFFFFF,\n\
\"uart_base_addr\": 0x10000000,\n\
\"uart_size\": 0x1000\n\
}" > "$(notdir $(BIN))_boot.cfg" && \
echo -e "\
{\n\
\"version\":1,\n\
\"machine\":\"riscv64\",\n\
\"memory_size\":256,\n\
\"bios\":\"$(shell pwd)/tb/dromajo/run/checkpoints/$(notdir $(BIN))/$(notdir $(BIN))\",\n\
\"load\":\"$(shell pwd)/tb/dromajo/run/checkpoints/$(notdir $(BIN))/$(notdir $(BIN))\",\n\
\"skip_commit\": [0x73, 0x9002, 0x100073],\n\
\"memory_base_addr\":0x80000000,\n\
\"clint_base_addr\": 0x02000000,\n\
\"clint_size\": 0xC0000,\n\
\"plic_base_addr\": 0x0C000000,\n\
\"plic_size\": 0x3FFFFFF,\n\
\"uart_base_addr\": 0x10000000,\n\
\"uart_size\": 0x1000\n\
}" > "$(notdir $(BIN)).cfg" && \
../../../src/dromajo --save=$(notdir $(BIN)) --save_format=1 ./$(notdir $(BIN))_boot.cfg && \
cd ../../../../../ && \
./work-ver/Variane_testharness +checkpoint=$(shell pwd)/tb/dromajo/run/checkpoints/$(notdir $(BIN))/$(notdir $(BIN))
corev_apu/tb/dpi/remote_bitbang.cc corev_apu/tb/dpi/msim_helper.cc
# User Verilator, at some point in the future this will be auto-generated
verilate: $(if $(DROMAJO), dromajo,)
verilate:
@echo "[Verilator] Building Model$(if $(PROFILE), for Profiling,)"
$(verilate_command)
cd $(ver-library) && $(MAKE) -j${NUM_JOBS} -f Variane_testharness.mk

21
README.md
View file

@ -80,7 +80,6 @@ CVA6 User Documentation
* [Going Beyond](#going-beyond)
* [CI Testsuites and Randomized Constrained Testing with Torture](#ci-testsuites-and-randomized-constrained-testing-with-torture)
* [Re-generating the Bootcode (ZSBL)](#re-generating-the-bootcode-zsbl)
* [Co-simulation with Dromajo](#co-simulation-with-dromajo)
* [Contributing](#contributing)
* [Acknowledgements](#acknowledgements)
@ -104,7 +103,7 @@ git submodule update --init --recursive
2. Run `./ci/setup.sh` to install all required tools (i.e. verilator, device-tree-compiler, riscv64-unknown-elf-*, ..)
You can install verilator from source using `./ci/install-verilator.sh` or by manually installing `verilator >= 4.002`
Note: There is currently a known issue with version 4.106 and 4.108. 4.106 does not compile and 4.108 hangs after a
Note: There is currently a known issue with version 4.106 and 4.108. 4.106 does not compile and 4.108 hangs after a
couple of cycles simulation time.)
@ -144,7 +143,7 @@ $ make veri_run
### Running User-Space Applications
It is possible to run user-space binaries on CVA6 with ([RISC-V Proxy Kernel and Boot Loader](https://github.com/riscv/riscv-pk)).
It is possible to run user-space binaries on CVA6 with ([RISC-V Proxy Kernel and Boot Loader](https://github.com/riscv/riscv-pk)).
RISC-V PK can be installed by running: `./ci/install-riscvpk.sh`
```
@ -422,22 +421,6 @@ The zero stage bootloader (ZSBL) for RTL simulation lives in `bootrom/` while th
To re-generate the bootcode you can use the existing makefile within those directories. To generate the SystemVerilog files you will need the `bitstring` python package installed on your system.
### Co-simulation with Dromajo
CVA6 can be co-simulated with [Dromajo](https://github.com/chipsalliance/dromajo) (currently in the verilator model).
```
make verilate DROMAJO=1
make run-dromajo-verilator BIN=/path/to/elf
```
The co-simulation flow is depicted in the figure below.
![image](https://user-images.githubusercontent.com/8511359/84510824-7ceb3b80-ac7a-11ea-9530-24c428ee87d9.png)
1. Load the binary of interest into Dromajo.
2. Run Dromajo stand alone and let a couple of instructions to complete.
3. Dump the checkpoint. This is the whole architectural state of the reference model. Dromajo dumps the main and boot memories. In addition, it generates a boot code. If you were to run that code it will restore the whole architectural state. This means that you can bring any two or more cores into complete synced architectural state by running this piece of code.
4. Load the checkpoint into the RTL memory and the instance of Dromajo in RTL. Dromajo gets linked to a simulator as a shared library. RTL communicates to Dromajo through set of DPI calls.
5. Run the RTL simulation and perform co-simulation.
# Contributing
Check out the [contribution guide](CONTRIBUTING.md)

36
common/local/util/sram.sv
View file

@ -24,8 +24,7 @@ module sram #(
parameter USER_EN = 0,
parameter NUM_WORDS = 1024,
parameter SIM_INIT = "none",
parameter OUT_REGS = 0, // enables output registers in FPGA macro (read lat = 2)
parameter DROMAJO_RAM = 0
parameter OUT_REGS = 0 // enables output registers in FPGA macro (read lat = 2)
)(
input logic clk_i,
input logic rst_ni,
@ -63,38 +62,6 @@ always_comb begin : p_align
end
for (genvar k = 0; k<(DATA_WIDTH+63)/64; k++) begin : gen_cut
if (DROMAJO_RAM) begin : gen_dromajo
dromajo_ram #(
.ADDR_WIDTH($clog2(NUM_WORDS)),
.DATA_DEPTH(NUM_WORDS),
.OUT_REGS (0)
) i_ram (
.Clk_CI ( clk_i ),
.Rst_RBI ( rst_ni ),
.CSel_SI ( req_i ),
.WrEn_SI ( we_i ),
.BEn_SI ( be_aligned[k*8 +: 8] ),
.WrData_DI ( wdata_aligned[k*64 +: 64] ),
.Addr_DI ( addr_i ),
.RdData_DO ( rdata_aligned[k*64 +: 64] )
);
if (USER_EN) begin : gen_dromajo_user
dromajo_ram #(
.ADDR_WIDTH($clog2(NUM_WORDS)),
.DATA_DEPTH(NUM_WORDS),
.OUT_REGS (0)
) i_ram_user (
.Clk_CI ( clk_i ),
.Rst_RBI ( rst_ni ),
.CSel_SI ( req_i ),
.WrEn_SI ( we_i ),
.BEn_SI ( be_aligned[k*8 +: 8] ),
.WrData_DI ( wuser_aligned[k*64 +: 64] ),
.Addr_DI ( addr_i ),
.RdData_DO ( ruser_aligned[k*64 +: 64] )
);
end
end else begin : gen_mem
// unused byte-enable segments (8bits) are culled by the tool
tc_sram_wrapper #(
.NumWords(NUM_WORDS), // Number of Words in data array
@ -136,6 +103,5 @@ end
end else begin
assign ruser_aligned[k*64 +: 64] = '0;
end
end
end
endmodule : sram

16
core/csr_regfile.sv
View file

@ -79,7 +79,7 @@ module csr_regfile import ariane_pkg::*; #(
output logic icache_en_o, // L1 ICache Enable
output logic dcache_en_o, // L1 DCache Enable
// Performance Counter
output logic [11:0] perf_addr_o, // read/write address to performance counter module
output logic [11:0] perf_addr_o, // read/write address to performance counter module
output logic[riscv::XLEN-1:0] perf_data_o, // write data to performance counter module
input logic[riscv::XLEN-1:0] perf_data_i, // read data from performance counter module
output logic perf_we_o,
@ -264,7 +264,7 @@ module csr_regfile import ariane_pkg::*; #(
riscv::CSR_MHPM_COUNTER_5,
riscv::CSR_MHPM_COUNTER_6,
riscv::CSR_MHPM_COUNTER_7,
riscv::CSR_MHPM_COUNTER_8,
riscv::CSR_MHPM_COUNTER_8,
riscv::CSR_MHPM_COUNTER_9,
riscv::CSR_MHPM_COUNTER_10,
riscv::CSR_MHPM_COUNTER_11,
@ -287,7 +287,7 @@ module csr_regfile import ariane_pkg::*; #(
riscv::CSR_MHPM_COUNTER_28,
riscv::CSR_MHPM_COUNTER_29,
riscv::CSR_MHPM_COUNTER_30,
riscv::CSR_MHPM_COUNTER_31 : csr_rdata = perf_data_i;
riscv::CSR_MHPM_COUNTER_31 : csr_rdata = perf_data_i;
riscv::CSR_MHPM_COUNTER_3H,
riscv::CSR_MHPM_COUNTER_4H,
@ -616,14 +616,14 @@ module csr_regfile import ariane_pkg::*; #(
riscv::CSR_MHPM_EVENT_5,
riscv::CSR_MHPM_EVENT_6,
riscv::CSR_MHPM_EVENT_7,
riscv::CSR_MHPM_EVENT_8 : begin perf_we_o = 1'b1; perf_data_o = csr_wdata;end
riscv::CSR_MHPM_EVENT_8 : begin perf_we_o = 1'b1; perf_data_o = csr_wdata;end
riscv::CSR_MHPM_COUNTER_3,
riscv::CSR_MHPM_COUNTER_4,
riscv::CSR_MHPM_COUNTER_5,
riscv::CSR_MHPM_COUNTER_6,
riscv::CSR_MHPM_COUNTER_7,
riscv::CSR_MHPM_COUNTER_8,
riscv::CSR_MHPM_COUNTER_8,
riscv::CSR_MHPM_COUNTER_9,
riscv::CSR_MHPM_COUNTER_10,
riscv::CSR_MHPM_COUNTER_11,
@ -646,7 +646,7 @@ module csr_regfile import ariane_pkg::*; #(
riscv::CSR_MHPM_COUNTER_28,
riscv::CSR_MHPM_COUNTER_29,
riscv::CSR_MHPM_COUNTER_30,
riscv::CSR_MHPM_COUNTER_31 : begin perf_we_o = 1'b1; perf_data_o = csr_wdata;end
riscv::CSR_MHPM_COUNTER_31 : begin perf_we_o = 1'b1; perf_data_o = csr_wdata;end
riscv::CSR_MHPM_COUNTER_3H,
riscv::CSR_MHPM_COUNTER_4H,
@ -1168,11 +1168,7 @@ module csr_regfile import ariane_pkg::*; #(
// floating-point registers
fcsr_q <= '0;
// debug signals
`ifdef DROMAJO
debug_mode_q <= 1'b1;
`else
debug_mode_q <= 1'b0;
`endif
dcsr_q <= '0;
dcsr_q.prv <= riscv::PRIV_LVL_M;
dcsr_q.xdebugver <= 4'h4;

51
core/cva6.sv
View file

@ -12,16 +12,6 @@
// Date: 19.03.2017
// Description: CVA6 Top-level module
`ifdef DROMAJO
import "DPI-C" function void dromajo_trap(int hart_id,
longint cause);
import "DPI-C" function void dromajo_step(int hart_id,
longint pc,
int insn,
longint wdata, longint cycle);
import "DPI-C" function void init_dromajo(string cfg_f_name);
`endif
module cva6 import ariane_pkg::*; #(
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig,
@ -891,51 +881,10 @@ module cva6 import ariane_pkg::*; #(
int f;
logic [63:0] cycles;
`ifdef DROMAJO
initial begin
string f_name;
if ($value$plusargs("checkpoint=%s", f_name)) begin
init_dromajo({f_name, ".cfg"});
$display("Done initing dromajo...");
end else begin
$display("Failed initing dromajo. Provide checkpoint name.");
end
end
`endif
initial begin
f = $fopen("trace_hart_00.dasm", "w");
end
`ifdef DROMAJO
always_ff @(posedge clk_i) begin
for (int i = 0; i < NR_COMMIT_PORTS; i++) begin
if (commit_instr_id_commit[i].ex.valid) begin
dromajo_trap(hart_id_i,
commit_instr_id_commit[i].ex.cause);
end
end
end
always_ff @(posedge clk_i) begin
for (int i = 0; i < NR_COMMIT_PORTS; i++) begin
if (commit_ack[i] && !commit_instr_id_commit[i].ex.valid) begin
if (csr_op_commit_csr == 0) begin
dromajo_step(hart_id_i,
commit_instr_id_commit[i].pc,
commit_instr_id_commit[i].ex.tval[31:0],
commit_instr_id_commit[i].result, cycles);
end else begin
dromajo_step(hart_id_i,
commit_instr_id_commit[i].pc,
commit_instr_id_commit[i].ex.tval[31:0],
csr_rdata_csr_commit, cycles);
end
end
end
end
`endif
always_ff @(posedge clk_i or negedge rst_ni) begin
if (~rst_ni) begin
cycles <= 0;

129
core/dromajo_ram.sv
View file

@ -1,129 +0,0 @@
// Copyright 2014 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
/**
* This is the copied and modified version of Inferable, Synchronous Single
* -Port N x 64bit RAM with Byte-Wise Enable to support dromajo cosimulation
*
* Current Maintainers:
* - Nursultan Kabylkas
*/
module dromajo_ram
#(
parameter ADDR_WIDTH = 10,
parameter DATA_DEPTH = 1024, // usually 2**ADDR_WIDTH, but can be lower
parameter OUT_REGS = 0 // set to 1 to enable outregs
)(
input logic Clk_CI,
input logic Rst_RBI,
input logic CSel_SI,
input logic WrEn_SI,
input logic [7:0] BEn_SI,
input logic [63:0] WrData_DI,
input logic [ADDR_WIDTH-1:0] Addr_DI,
output logic [63:0] RdData_DO
);
////////////////////////////
// signals, localparams
////////////////////////////
// needs to be consistent with the Altera implemenation below
localparam DATA_BYTES = 8;
logic [DATA_BYTES*8-1:0] RdData_DN;
logic [DATA_BYTES*8-1:0] RdData_DP;
logic [DATA_BYTES*8-1:0] Mem_DP[DATA_DEPTH-1:0];
////////////////////////////
// DROMAJO COSIM OPTION
// sync rams
////////////////////////////\
initial begin
integer hex_file, num_bytes;
longint address, value;
string f_name;
// init to 0
for (int k=0; k<DATA_DEPTH; k++) begin
Mem_DP[k] = 0;
end
// sync with dromajo
if ($value$plusargs("checkpoint=%s", f_name)) begin
hex_file = $fopen({f_name,".mainram.hex"}, "r");
while (!$feof(hex_file)) begin
num_bytes = $fscanf(hex_file, "%d %h\n", address, value);
//$display("%d %h", address, value);
Mem_DP[address] = value;
end
$display("Done syncing RAM with dromajo...\n");
end else begin
$display("Failed syncing RAM: provide path to a checkpoint.\n");
end
end
always @(posedge Clk_CI) begin
if(CSel_SI) begin
if(WrEn_SI) begin
if(BEn_SI[0]) Mem_DP[Addr_DI][7:0] <= WrData_DI[7:0];
if(BEn_SI[1]) Mem_DP[Addr_DI][15:8] <= WrData_DI[15:8];
if(BEn_SI[2]) Mem_DP[Addr_DI][23:16] <= WrData_DI[23:16];
if(BEn_SI[3]) Mem_DP[Addr_DI][31:24] <= WrData_DI[31:24];
if(BEn_SI[4]) Mem_DP[Addr_DI][39:32] <= WrData_DI[39:32];
if(BEn_SI[5]) Mem_DP[Addr_DI][47:40] <= WrData_DI[47:40];
if(BEn_SI[6]) Mem_DP[Addr_DI][55:48] <= WrData_DI[55:48];
if(BEn_SI[7]) Mem_DP[Addr_DI][63:56] <= WrData_DI[63:56];
end
RdData_DN <= Mem_DP[Addr_DI];
end
end
////////////////////////////
// optional output regs
////////////////////////////
// output regs
generate
if (OUT_REGS>0) begin : g_outreg
always_ff @(posedge Clk_CI or negedge Rst_RBI) begin
if(Rst_RBI == 1'b0)
begin
RdData_DP <= 0;
end
else
begin
RdData_DP <= RdData_DN;
end
end
end
endgenerate // g_outreg
// output reg bypass
generate
if (OUT_REGS==0) begin : g_oureg_byp
assign RdData_DP = RdData_DN;
end
endgenerate// g_oureg_byp
assign RdData_DO = RdData_DP;
////////////////////////////
// assertions
////////////////////////////
// pragma translate_off
assert property
(@(posedge Clk_CI) (longint'(2)**longint'(ADDR_WIDTH) >= longint'(DATA_DEPTH)))
else $error("depth out of bounds");
// pragma translate_on
endmodule //dromajo_ram

62
corev_apu/bootrom/dromajo_bootrom.sv
View file

@ -1,62 +0,0 @@
/* Copyright 2020 ETH Zurich and University of Bologna.
* Copyright and related rights are licensed under the Solderpad Hardware
* License, Version 0.51 (the "License"); you may not use this file except in
* compliance with the License. You may obtain a copy of the License at
* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
* or agreed to in writing, software, hardware and materials distributed under
* this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
* CONDITIONS OF ANY KIND, either express or implied. See the License for the
* specific language governing permissions and limitations under the License.
*
* File: dromajo_bootrom.sv
*
* Author: Nursultan Kabylkas, UCSC
* Description: bootrom that gets synced with dromajo for
* cosimulation purposes.
*/
module dromajo_bootrom (
input logic clk_i,
input logic req_i,
input logic [63:0] addr_i,
output logic [63:0] rdata_o
);
localparam int RomSize = 4096;
logic [63:0] mem[RomSize-1:0];
initial begin
integer hex_file, num_bytes;
longint address, value;
string f_name;
// init to 0
for (int k=0; k<RomSize; k++) begin
mem[k] = 0;
end
// sync with dromajo
if ($value$plusargs("checkpoint=%s", f_name)) begin
hex_file = $fopen({f_name,".bootram.hex"}, "r");
while (!$feof(hex_file)) begin
num_bytes = $fscanf(hex_file, "%d %h\n", address, value);
//$display("%d %h", address, value);
mem[address] = value;
end
$display("Done syncing boot ROM with dromajo...\n");
end else begin
$display("Failed syncing boot ROM: provide path to a checkpoint.\n");
end
end
logic [$clog2(RomSize)-1:0] addr_q;
always_ff @(posedge clk_i) begin
if (req_i) begin
addr_q <= addr_i[$clog2(RomSize)-1+3:3];
end
end
// this prevents spurious Xes from propagating into
// the speculative fetch stage of the core
assign rdata_o = (addr_q < RomSize) ? mem[addr_q] : '0;
endmodule

28
corev_apu/tb/ariane_tb.cpp
View file

@ -55,14 +55,12 @@ static vluint64_t main_time = 0;
static const char *verilog_plusargs[] = {"jtag_rbb_enable", "time_out", "debug_disable"};
#ifndef DROMAJO
extern dtm_t* dtm;
extern remote_bitbang_t * jtag;
void handle_sigterm(int sig) {
dtm->stop();
}
#endif
// Called by $time in Verilog converts to double, to match what SystemC does
double sc_time_stamp () {
@ -181,9 +179,6 @@ int main(int argc, char **argv) {
case 'r': rbb_port = atoi(optarg); break;
case 'V': verbose = true; break;
case 'p': perf = true; break;
#ifdef DROMAJO
case 'D': break;
#endif
#if VM_TRACE
case 'v': {
vcdfile = strcmp(optarg, "-") == 0 ? stdout : fopen(optarg, "w");
@ -213,12 +208,6 @@ int main(int argc, char **argv) {
c = 'm';
optarg = optarg+12;
}
#ifdef DROMAJO
else if (arg.substr(0, 12) == "+checkpoint=") {
c = 'D';
optarg = optarg+12;
}
#endif
#if VM_TRACE
else if (arg.substr(0, 12) == "+dump-start=") {
c = 'x';
@ -277,15 +266,11 @@ int main(int argc, char **argv) {
}
done_processing:
// allow proceeding without a binary if DROMAJO set,
// binary will be loaded through checkpoint
#ifndef DROMAJO
if (optind == argc) {
std::cerr << "No binary specified for emulator\n";
usage(argv[0]);
return 1;
}
#endif
int htif_argc = 1 + argc - optind;
htif_argv = (char **) malloc((htif_argc) * sizeof (char *));
htif_argv[0] = argv[0];
@ -294,11 +279,9 @@ done_processing:
const char *vcd_file = NULL;
Verilated::commandArgs(argc, argv);
#ifndef DROMAJO
jtag = new remote_bitbang_t(rbb_port);
dtm = new preload_aware_dtm_t(htif_argc, htif_argv);
signal(SIGTERM, handle_sigterm);
#endif
std::unique_ptr<Variane_testharness> top(new Variane_testharness);
@ -355,19 +338,14 @@ done_processing:
size_t mem_size = 0xFFFFFF;
#if (VERILATOR_VERSION_INTEGER >= 5000000)
// Verilator v5: Use rootp pointer and .data() accessor.
memif.read(0x80000000, mem_size, (void *)top->rootp->ariane_testharness__DOT__i_sram__DOT__gen_cut__BRA__0__KET____DOT__gen_mem__DOT__i_tc_sram_wrapper__DOT__i_tc_sram__DOT__sram.data());
memif.read(0x80000000, mem_size, (void *)top->rootp->ariane_testharness__DOT__i_sram__DOT__gen_cut__BRA__0__KET____DOT__i_tc_sram_wrapper__DOT__i_tc_sram__DOT__sram.data());
#else
// Verilator v4
memif.read(0x80000000, mem_size, (void *)top->ariane_testharness__DOT__i_sram__DOT__gen_cut__BRA__0__KET____DOT__gen_mem__DOT__i_tc_sram_wrapper__DOT__i_tc_sram__DOT__sram);
memif.read(0x80000000, mem_size, (void *)top->ariane_testharness__DOT__i_sram__DOT__gen_cut__BRA__0__KET____DOT__i_tc_sram_wrapper__DOT__i_tc_sram__DOT__sram);
#endif
// memif.read(0x84000000, mem_size, (void *)top->ariane_testharness__DOT__i_sram__DOT__gen_cut__BRA__0__KET____DOT__gen_mem__DOT__gen_mem_user__DOT__i_tc_sram_wrapper_user__DOT__i_tc_sram__DOT__sram);
#ifndef DROMAJO
while (!dtm->done() && !jtag->done() && !(top->exit_o & 0x1)) {
#else
// the simulation gets killed by dromajo
while (true) {
#endif
top->clk_i = 0;
top->eval();
#if VM_TRACE
@ -395,7 +373,6 @@ done_processing:
fclose(vcdfile);
#endif
#ifndef DROMAJO
if (dtm->exit_code()) {
fprintf(stderr, "%s *** FAILED *** (tohost = %d) after %ld cycles\n", htif_argv[1], dtm->exit_code(), main_time);
ret = dtm->exit_code();
@ -412,7 +389,6 @@ done_processing:
if (dtm) delete dtm;
if (jtag) delete jtag;
#endif
std::clock_t c_end = std::clock();
auto t_end = std::chrono::high_resolution_clock::now();

2
corev_apu/tb/ariane_tb.sv
View file

@ -19,7 +19,7 @@ import uvm_pkg::*;
`include "uvm_macros.svh"
`define MAIN_MEM(P) dut.i_sram.gen_cut[0].gen_mem.i_tc_sram_wrapper.i_tc_sram.init_val[(``P``)]
`define MAIN_MEM(P) dut.i_sram.gen_cut[0].i_tc_sram_wrapper.i_tc_sram.init_val[(``P``)]
// `define USER_MEM(P) dut.i_sram.gen_cut[0].gen_mem.gen_mem_user.i_tc_sram_wrapper_user.i_tc_sram.init_val[(``P``)]
import "DPI-C" function read_elf(input string filename);

16
corev_apu/tb/ariane_testharness.sv
View file

@ -20,11 +20,7 @@ module ariane_testharness #(
parameter int unsigned AXI_USER_EN = ariane_pkg::AXI_USER_EN,
parameter int unsigned AXI_ADDRESS_WIDTH = 64,
parameter int unsigned AXI_DATA_WIDTH = 64,
`ifdef DROMAJO
parameter bit InclSimDTM = 1'b0,
`else
parameter bit InclSimDTM = 1'b1,
`endif
parameter int unsigned NUM_WORDS = 2**25, // memory size
parameter bit StallRandomOutput = 1'b0,
parameter bit StallRandomInput = 1'b0
@ -343,21 +339,12 @@ module ariane_testharness #(
.data_i ( rom_rdata )
);
`ifdef DROMAJO
dromajo_bootrom i_bootrom (
.clk_i ( clk_i ),
.req_i ( rom_req ),
.addr_i ( rom_addr ),
.rdata_o ( rom_rdata )
);
`else
bootrom i_bootrom (
.clk_i ( clk_i ),
.req_i ( rom_req ),
.addr_i ( rom_addr ),
.rdata_o ( rom_rdata )
);
`endif
// ------------------------------
// GPIO
@ -465,9 +452,6 @@ module ariane_testharness #(
.SIM_INIT ( "none" ),
`else
.SIM_INIT ( "zeros" ),
`endif
`ifdef DROMAJO
.DROMAJO_RAM (1),
`endif
.NUM_WORDS ( NUM_WORDS )
) i_sram (

102
corev_apu/tb/dpi/dromajo_cosim_dpi.cc
View file

@ -1,102 +0,0 @@
// Copyright 2017-2020 ETH Zurich and University of Bologna.
// Copyright and related rights are licensed under the Solderpad Hardware
// License, Version 0.51 (the "License"); you may not use this file except in
// compliance with the License. You may obtain a copy of the License at
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
// or agreed to in writing, software, hardware and materials distributed under
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
// specific language governing permissions and limitations under the License.
//
// Author: Nursultan Kabylkas, UCSC
// Date: Jun 15, 2020
// Description: DPI wrappers to interface with Dromajo RISC-V emulator
#include <svdpi.h>
#include <iostream>
#include "dromajo_cosim.h"
#include "stdlib.h"
#include <string>
#include <vector>
/**
* pointer to the dromajo emulator this pointer gets
* accessed from RTL
*/
dromajo_cosim_state_t* dromajo_pointer;
/**
* set the counter variable to number of instructions
* you want to commit after the cosim failure. This is
* sometimes useful when debugging to see waveform
* activity post failure
*/
bool kill_soon = false;
uint32_t counter = 0;
/**
* Initialize dromajo emulator
*
* This function should usually be called from the initial
* block in RTL.
*
* @param config (.cfg) file with the configurations
*/
extern "C" void init_dromajo(char* cfg_f_name) {
char *argv[] = {(char*)"Variane", cfg_f_name};
dromajo_pointer = dromajo_cosim_init(2, argv);
}
/**
* Progress the emulator
*
* This function progresses the emulator by one instruction
* and compares the results by the committed instruction
* in RTL. The following parameters are passed from RTL to
* dromajo for comparison purposes.
*
* @param hart_id - id of the HART that is commiting instruction
* @param pc - pc of the instruction being committed
* @param insn - RISCV instruction being committed
* @param wdata - the value being committed (what's going to destination register)
* @param cycle - clock cycle number (optional, this is not compared)
*/
extern "C" void dromajo_step(int hart_id,
uint64_t pc,
uint32_t insn,
uint64_t wdata,
uint64_t cycle) {
int exit_code;
do {
exit_code = dromajo_cosim_step(dromajo_pointer, hart_id, pc, insn, wdata, 0, true);
} while (exit_code == 0x3);
if (exit_code > 3) {
kill_soon = true;
} else if (exit_code == 0x2){
exit(0);
}
if (kill_soon) {
if (counter == 0) {
std::cout << "Cosim failed!" << std::endl;
exit(1);
} else {
std::cout << "Let's let it run for a couple of instructions" << std::endl;
}
counter--;
}
}
/**
* Redirects dromajo's execution flow on exception/interrupt
*
* @param hart_id - id of the HART that is trapping
* @param cause - exception or interrupt cause
*/
extern "C" void dromajo_trap(int hart_id,
uint64_t cause) {
std::cout << "Dromajo trapping. Cause = " << cause << std::endl;
dromajo_cosim_raise_trap(dromajo_pointer, hart_id, cause);
}

1
corev_apu/tb/dromajo

@ -1 +0,0 @@
Subproject commit 8acade8725d5e6cbf373304b348a8d77e0a5c713