docs: add CV32A60X configuration in RISC-V ISA manual (#2806)

* docs: spec_builder.py: add missing extensions
* docs: fix unpriv manual (opcode map, Zcmop)
- in opcode map, write not used when corresponding extension is disabled
- use correct condition for Zcmop extension
* docs: remove PMP chapter when no PMP
* docs: add tailored RISC-V ISA manual for CV32A60X configuration

docs/scripts/spec_builder.py

@@ -51,14 +51,24 @@ DEFAULT_PARAMS = {
     'RVZabha': False,
     'RVZacas': False,
     'RVZawrs': False,
+    'RVZcmop': False,
     'RVZfa': False,
     'RVZfbf-RZvfbf': False,
     'RVZfh': False,
     'RVZfinx': False,
     'RVZicbo': False,
     'RVZicfilp': False,
+    'RVZifencei': False,
+    'RVZihintntl': False,
+    'RVZihintpause': False,
+    'RVZimop': False,
+    'RVZk': False,
     'RVZpm': False,
+    'RVZsmcdeleg': False,
+    'RVZsmcntrpmf': False,
+    'RVZsmcsrind-RVZsscsrind': False,
     'RVZsmctr': False,
+    'RVZsmdbltrp': False,
     'RVZsmepmp': False,
     'RVZsmmpm': False,
     'RVZsmrnmi': False,