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small byte enable fixes in dm

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This commit is contained in:
Michael Schaffner 2018-08-23 16:47:41 +02:00
parent 5e7734559f
commit 5c5e37fc25
3 changed files with 17 additions and 7 deletions
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2
src/csr_regfile.sv
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@ -146,7 +146,7 @@ module csr_regfile #(
if (csr_read) begin
case (csr_addr.address)
// debug registers
riscv::CSR_DCSR: csr_rdata = {31'b0, dcsr_q};
riscv::CSR_DCSR: csr_rdata = {32'b0, dcsr_q};
riscv::CSR_DPC: csr_rdata = dpc_q;
riscv::CSR_DSCRATCH0: csr_rdata = dscratch0_q;
// trigger module registers

3
src/debug/dm_csrs.sv
View file

@ -184,7 +184,7 @@ module dm_csrs #(
command_d = command_q;
progbuf_d = progbuf_q;
data_d = data_q;
sbcs_d = sbcs_d;
sbcs_d = sbcs_q;
sbaddr_d = sbaddress_i;
sbdata_d = sbdata_q;
@ -426,6 +426,7 @@ module dm_csrs #(
sbcs_d.sbaccess32 = 1'b0;
sbcs_d.sbaccess16 = 1'b0;
sbcs_d.sbaccess8 = 1'b0;
sbcs_d.sbaccess = 1'b0;
end
// output multiplexer

19
src/debug/dm_sba.sv
View file

@ -49,7 +49,7 @@ module dm_sba (
logic req;
logic gnt;
logic we;
logic [7:0][7:0] be;
logic [7:0] be;
assign sbbusy_o = (state_q != Idle) ? 1'b1 : 1'b0;
@ -86,8 +86,8 @@ module dm_sba (
// generate byte enable mask
case (sbaccess_i)
3'b000: be[ sbaddress_i[2:0]] = '1;
3'b001: be[{sbaddress_i[2:1], 1'b0} +: 1] = '1;
3'b010: be[{sbaddress_i[2:2], 2'b0} +: 3] = '1;
3'b001: be[{sbaddress_i[2:1], 1'b0} +: 2] = '1;
3'b010: be[{sbaddress_i[2:2], 2'b0} +: 4] = '1;
3'b011: be = '1;
default:;
endcase
@ -131,7 +131,7 @@ module dm_sba (
axi_adapter #(
.DATA_WIDTH ( 64 )
) i_axi_master (
.clk_i,
.clk_i ( clk_i ),
.rst_ni ( dmactive_i ),
.req_i ( req ),
.type_i ( std_cache_pkg::SINGLE_REQ),
@ -141,7 +141,7 @@ module dm_sba (
.we_i ( we ),
.wdata_i ( sbdata_i ),
.be_i ( be ),
.size_i ( sbaccess_i ),
.size_i ( sbaccess_i[1:0] ),
.id_i ( '0 ),
.valid_o ( sbdata_valid_o ),
.rdata_o ( sbdata_o ),
@ -150,4 +150,13 @@ module dm_sba (
.critical_word_valid_o ( ), // not needed here
.axi ( axi_master )
);
`ifndef SYNTHESIS
`ifndef verilator
// maybe bump severity to $error if not handled at runtime
dm_sba_access_size: assert property(@(posedge clk_i) disable iff (dmactive_i !== 1'b0) (state_d != Idle) |-> (sbaccess_i < 4)) else $warning ("accesses > 8 byte not supported at the moment");
`endif
`endif
endmodule