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Merge bit enable for valid/dirty flags
Merge bit enable for valid/dirty flags
This commit is contained in:
msfschaffner
Florian Zaruba
parent
dbd1cf657d
commit
5c7aa67cc0
5 changed files with 30 additions and 76 deletions
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@ -56,10 +56,9 @@ package std_cache_pkg;
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// cache line byte enable
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typedef struct packed {
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logic [(ariane_pkg::DCACHE_TAG_WIDTH+7)/8-1:0] tag; // byte enable into tag array
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logic [(ariane_pkg::DCACHE_LINE_WIDTH+7)/8-1:0] data; // byte enable into data array
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logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] dirty; // byte enable into state array
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logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] valid; // byte enable into state array
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logic [(ariane_pkg::DCACHE_TAG_WIDTH+7)/8-1:0] tag; // byte enable into tag array
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logic [(ariane_pkg::DCACHE_LINE_WIDTH+7)/8-1:0] data; // byte enable into data array
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logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] vldrty; // bit enable into state array (valid for a pair of dirty/valid bits)
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} cl_be_t;
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// convert one hot to bin for -> needed for cache replacement
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@ -283,9 +283,8 @@ module cache_ctrl #(
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addr_o = mem_req_q.index;
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we_o = 1'b1;
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be_o.dirty = hit_way_q;
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be_o.valid = hit_way_q;
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be_o.vldrty = hit_way_q;
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// set the correct byte enable
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be_o.data[cl_offset>>3 +: 8] = mem_req_q.be;
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data_o.data[cl_offset +: 64] = mem_req_q.wdata;
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@ -233,8 +233,7 @@ module miss_handler #(
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req_o = evict_way_q;
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we_o = 1'b1;
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be_o = '1;
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be_o.valid = evict_way_q;
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be_o.dirty = evict_way_q;
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be_o.vldrty = evict_way_q;
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data_o.tag = mshr_q.addr[DCACHE_TAG_WIDTH+DCACHE_INDEX_WIDTH-1:DCACHE_INDEX_WIDTH];
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data_o.data = data_miss_fsm;
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data_o.valid = 1'b1;
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@ -277,8 +276,7 @@ module miss_handler #(
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req_o = 1'b1;
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we_o = 1'b1;
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// invalidate
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be_o.valid = evict_way_q;
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be_o.dirty = evict_way_q;
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be_o.vldrty = evict_way_q;
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// go back to handling the miss or flushing, depending on where we came from
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state_d = (state_q == WB_CACHELINE_MISS) ? MISS : FLUSH_REQ_STATUS;
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end
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@ -305,12 +303,12 @@ module miss_handler #(
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// not dirty ~> increment and continue
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end else begin
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// increment and re-request
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cnt_d = cnt_q + (1'b1 << DCACHE_BYTE_OFFSET);
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state_d = FLUSH_REQ_STATUS;
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addr_o = cnt_q;
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req_o = 1'b1;
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be_o.valid = '1;
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we_o = 1'b1;
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cnt_d = cnt_q + (1'b1 << DCACHE_BYTE_OFFSET);
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state_d = FLUSH_REQ_STATUS;
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addr_o = cnt_q;
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req_o = 1'b1;
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be_o.vldrty = '1;
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we_o = 1'b1;
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// finished with flushing operation, go back to idle
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if (cnt_q[DCACHE_INDEX_WIDTH-1:DCACHE_BYTE_OFFSET] == DCACHE_NUM_WORDS-1) begin
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flush_ack_o = 1'b1;
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@ -326,9 +324,8 @@ module miss_handler #(
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req_o = 1'b1;
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we_o = 1'b1;
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// only write the dirty array
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be_o.dirty = '1;
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be_o.valid = '1;
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cnt_d = cnt_q + (1'b1 << DCACHE_BYTE_OFFSET);
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be_o.vldrty = '1;
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cnt_d = cnt_q + (1'b1 << DCACHE_BYTE_OFFSET);
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// finished initialization
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if (cnt_q[DCACHE_INDEX_WIDTH-1:DCACHE_BYTE_OFFSET] == DCACHE_NUM_WORDS-1)
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state_d = IDLE;
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@ -182,7 +182,7 @@ module std_nbdcache #(
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.we_i ( we_ram ),
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.addr_i ( addr_ram[DCACHE_INDEX_WIDTH-1:DCACHE_BYTE_OFFSET] ),
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.wdata_i ( wdata_ram.tag ),
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.be_i ( be_ram.tag ),
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.be_i ( be_ram.tag ),
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.rdata_o ( rdata_ram[i].tag ),
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.*
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);
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@ -192,26 +192,30 @@ module std_nbdcache #(
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// ----------------
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// Valid/Dirty Regs
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// ----------------
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logic [DCACHE_DIRTY_WIDTH-1:0] dirty_wdata, dirty_rdata;
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// align each valid/dirty bit pair to a byte boundary in order to leverage byte enable signals.
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// note: if you have an SRAM that supports flat bit enables for your target technology,
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// you can use it here to save the extra 4x overhead introduced by this workaround.
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logic [4*DCACHE_DIRTY_WIDTH-1:0] dirty_wdata, dirty_rdata;
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for (genvar i = 0; i < DCACHE_SET_ASSOC; i++) begin
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assign dirty_wdata[i] = wdata_ram.dirty;
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assign dirty_wdata[DCACHE_SET_ASSOC + i] = wdata_ram.valid;
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assign rdata_ram[i].valid = dirty_rdata[DCACHE_SET_ASSOC + i];
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assign rdata_ram[i].dirty = dirty_rdata[i];
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assign dirty_wdata[8*i] = wdata_ram.dirty;
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assign dirty_wdata[8*i+1] = wdata_ram.valid;
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assign rdata_ram[i].dirty = dirty_rdata[8*i];
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assign rdata_ram[i].valid = dirty_rdata[8*i+1];
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end
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vdregs #(
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.DATA_WIDTH ( DCACHE_DIRTY_WIDTH ),
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.DATA_DEPTH ( DCACHE_NUM_WORDS )
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) i_vdregs (
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sram #(
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.DATA_WIDTH ( 4*DCACHE_DIRTY_WIDTH ),
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.NUM_WORDS ( DCACHE_NUM_WORDS )
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) valid_dirty_sram (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.req_i ( |req_ram ),
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.we_i ( we_ram ),
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.addr_i ( addr_ram[DCACHE_INDEX_WIDTH-1:DCACHE_BYTE_OFFSET] ),
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.wdata_i ( dirty_wdata ),
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.biten_i ( {be_ram.valid, be_ram.dirty} ),
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.be_i ( be_ram.vldrty ),
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.rdata_o ( dirty_rdata )
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);
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@ -1,45 +0,0 @@
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// Copyright 2018 ETH Zurich and University of Bologna.
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the "License"); you may not use this file except in
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// compliance with the License. You may obtain a copy of the License at
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// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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// or agreed to in writing, software, hardware and materials distributed under
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// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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//
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// Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>, ETH Zurich
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// Michael Schaffner <schaffner@iis.ee.ethz.ch>, ETH Zurich
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// Date: 15.08.2018
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// Description: valid/dirty regfile for caches
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//
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module vdregs #(
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parameter DATA_WIDTH = 64,
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parameter DATA_DEPTH = 1024
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)(
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input logic clk_i,
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input logic rst_ni,
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input logic req_i,
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input logic we_i,
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input logic [$clog2(DATA_DEPTH)-1:0] addr_i,
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input logic [DATA_WIDTH-1:0] wdata_i,
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input logic [DATA_WIDTH-1:0] biten_i, // bit enable
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output logic [DATA_WIDTH-1:0] rdata_o
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);
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localparam ADDR_WIDTH = $clog2(DATA_DEPTH);
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logic [DATA_WIDTH-1:0] regs_q [DATA_DEPTH-1:0];
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if(~rst_ni) begin
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regs_q <= '{default:0};
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end else if (req_i) begin
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if (we_i) begin
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for (int i = 0; i < DATA_WIDTH; i++)
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if (biten_i[i]) regs_q[addr_i][i] <= wdata_i[i];
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end
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rdata_o <= regs_q[addr_i];
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end
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end
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endmodule : vdregs
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