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https://github.com/openhwgroup/cva6.git
synced 2025-04-19 11:54:46 -04:00
Fix log naming and dashboard improvements (#2001)
This commit is contained in:
valentinThomazic
GitHub
parent
73e181cdef
commit
5c7ddcbcc5
3 changed files with 40 additions and 28 deletions
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@ -132,6 +132,7 @@ smoke:
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DASHBOARD_SORT_INDEX: 0
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DASHBOARD_JOB_CATEGORY: "Basic"
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SPIKE_TANDEM: 1
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COLLECT_SIMU_LOGS: 1
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parallel:
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matrix:
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- DV_SIMULATORS:
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@ -151,6 +152,7 @@ gen_smoke:
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DASHBOARD_SORT_INDEX: 0
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DASHBOARD_JOB_CATEGORY: "Basic"
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DV_SIMULATORS: "vcs-uvm,spike"
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COLLECT_SIMU_LOGS: 1
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script:
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- bash verif/regress/smoke-gen_tests.sh
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- !reference [.simu_after_script]
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@ -242,9 +244,7 @@ fpga-build:
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- source $VIVADO_SETUP
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- source ./verif/sim/setup-env.sh
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- mkdir -p artifacts/logs
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- make fpga target=$TARGET &> artifacts/logs/logfile.log
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- tail -20 artifacts/logs/logfile.log > artifacts/logs/logfile.log.tail
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- rm -f artifacts/logs/logfile.log
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- make fpga target=$TARGET |& tail -20 > artifacts/logs/logfile.log.tail
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- mkdir -p artifacts/reports
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- mv corev_apu/fpga/work-fpga/ariane_xilinx.bit artifacts/ariane_xilinx_$TARGET.bit
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- python3 .gitlab-ci/scripts/report_fpga.py corev_apu/fpga/reports/ariane.utilization.rpt artifacts/logs/logfile.log.tail
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@ -280,6 +280,7 @@ riscv_arch_test:
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DASHBOARD_SORT_INDEX: 0
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DASHBOARD_JOB_CATEGORY: "Test suites"
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DV_SIMULATORS: "veri-testharness,spike"
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COLLECT_SIMU_LOGS: 1
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script: source verif/regress/dv-riscv-arch-test.sh
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after_script: *simu_after_script
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@ -292,6 +293,7 @@ compliance:
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DASHBOARD_SORT_INDEX: 2
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DASHBOARD_JOB_CATEGORY: "Test suites"
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DV_SIMULATORS: "veri-testharness,spike"
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COLLECT_SIMU_LOGS: 1
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script: source verif/regress/dv-riscv-compliance.sh
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after_script: *simu_after_script
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@ -306,6 +308,7 @@ riscv-tests-v:
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DV_SIMULATORS: "veri-testharness,spike"
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DV_TARGET: cv64a6_imafdc_sv39
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DV_TESTLISTS: "../tests/testlist_riscv-tests-$DV_TARGET-v.yaml"
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COLLECT_SIMU_LOGS: 1
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script: source verif/regress/dv-riscv-tests.sh
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after_script: *simu_after_script
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@ -319,6 +322,7 @@ riscv-tests-p:
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DASHBOARD_JOB_CATEGORY: "Test suites"
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DV_SIMULATORS: "veri-testharness,spike"
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DV_TESTLISTS: "../tests/testlist_riscv-tests-$DV_TARGET-p.yaml"
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COLLECT_SIMU_LOGS: 1
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script: source verif/regress/dv-riscv-tests.sh
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after_script: *simu_after_script
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@ -15,8 +15,10 @@ import os
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with open(str(sys.argv[1]), 'r') as f:
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log = f.read()
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with_logs = os.environ.get("COLLECT_SIMU_LOGS") != None
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pattern = re.compile(
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r'(?:\w{3}, \d{2} \w{3} \d{4} \d{2}:\d{2}:\d{2} INFO )Compiling (.*): .*(tests\S*)$[\s\S]*?^(?:\w{3}, \d{2} \w{3} \d{4} \d{2}:\d{2}:\d{2} INFO )Found matching ISS: (\S*)$[\s\S]*?^(?:\w{3}, \d{2} \w{3} \d{4} \d{2}:\d{2}:\d{2} INFO )Target: (\S*)$[\s\S]*?^(?:\w{3}, \d{2} \w{3} \d{4} \d{2}:\d{2}:\d{2}(?: INFO ))ISA (\S*)$[\s\S]*?^(?:\w{3}, \d{2} \w{3} \d{4} \d{2}:\d{2}:\d{2} (?:(?:INFO )\[(\w*)\]: (\d*) matched(?:, (\d*) mismatch)?)|(?:^(?:\w{3}, \d{2} \w{3} \d{4} \d{2}:\d{2}:\d{2})(?: ERROR )(\D{5})(?:.*)$))',
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r'(?:\w{3}, \d{2} \w{3} \d{4} \d{2}:\d{2}:\d{2} INFO )(?:Processing regression test list : (?:.*)/testlist_(.*-.*)(?:.yaml), test: (\S*)$[\s\S]*?^(?:\w{3}, \d{2} \w{3} \d{4} \d{2}:\d{2}:\d{2} INFO )Compiling (.*):.*$|Compiling (.*): .*(tests\S*))$[\s\S]*?^(?:\w{3}, \d{2} \w{3} \d{4} \d{2}:\d{2}:\d{2} INFO )Found matching ISS: (\S*)$[\s\S]*?^(?:\w{3}, \d{2} \w{3} \d{4} \d{2}:\d{2}:\d{2} INFO )Target: (\S*)$[\s\S]*?^(?:\w{3}, \d{2} \w{3} \d{4} \d{2}:\d{2}:\d{2}(?: INFO ))ISA (\S*)$[\s\S]*?^(?:\w{3}, \d{2} \w{3} \d{4} \d{2}:\d{2}:\d{2} (?:(?:INFO )\[(\w*)\]: (\d*) matched(?:, (\d*) mismatch)?)|(?:^(?:\w{3}, \d{2} \w{3} \d{4} \d{2}:\d{2}:\d{2})(?: ERROR )(\D{5})(?:.*)$))',
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re.MULTILINE)
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list_of_tests = pattern.findall(log)
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@ -24,32 +26,36 @@ metric = rb.TableStatusMetric('')
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metric.add_column("TARGET", "text")
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metric.add_column("ISA", "text")
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metric.add_column("TEST_TYPE", "text")
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metric.add_column("TEST", "text")
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metric.add_column("OUTPUT", "log")
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metric.add_column("TB_LOGS", "log")
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metric.add_column("DISASSEMBLY", "log")
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metric.add_column("TEST LIST", "text")
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if with_logs:
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metric.add_column("OUTPUT", "log")
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metric.add_column("TB LOGS", "log")
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metric.add_column("DISASSEMBLY", "log")
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job_test_pass = 0
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job_test_total = 0
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logsPath = "logs/" + os.environ.get("CI_JOB_ID") + "/artifacts/logs/"
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for i in list_of_tests:
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job_test_total += 1
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target = i[3]
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isa = i[4]
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testsuite = i[0]
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test = i[1].split("/")[-1].split(".")[0]
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target = i[6]
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isa = i[7]
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test = i[1] or i[4].split("/")[-1].split(".")[0]
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testsuite = i[0] or "custom test"
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test_type = i[2] or i[4]
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output_log = logsPath + 'logfile.log.head'
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tb_log = logsPath + test + "." + target + '.log.iss.head'
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disassembly = logsPath + test + "." + target + '.csv.head'
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if with_logs:
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logsPath = "logs/" + os.environ.get("CI_JOB_ID") + "/artifacts/logs/"
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output_log = logsPath + 'logfile.log.head'
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tb_log = logsPath + test + "." + target + '.log.iss.head'
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disassembly = logsPath + test + "." + target + '.csv.head'
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col = [target, isa, test, testsuite, output_log, tb_log, disassembly]
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else:
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col = [target, isa, test, testsuite]
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col = [target, isa, testsuite, test, output_log, tb_log, disassembly]
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if i[5] == "PASSED":
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if i[8] == "PASSED":
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metric.add_pass(*col)
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job_test_pass += 1
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else:
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@ -411,7 +411,7 @@ def gcc_compile(test_list, output_dir, isa, mabi, opts, debug_cmd, linker):
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def run_assembly(asm_test, iss_yaml, isa, target, mabi, gcc_opts, iss_opts, output_dir,
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setting_dir, debug_cmd, linker, priv, spike_params):
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setting_dir, debug_cmd, linker, priv, spike_params, test_name = None):
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"""Run a directed assembly test with ISS
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Args:
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@ -455,12 +455,13 @@ def run_assembly(asm_test, iss_yaml, isa, target, mabi, gcc_opts, iss_opts, outp
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elf2bin(elf, binary, debug_cmd)
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log_list = []
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# ISS simulation
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test_log_name = test_name or asm
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for iss in iss_list:
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run_cmd("mkdir -p %s/%s_sim" % (output_dir, iss))
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if log_format == 1:
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log = ("%s/%s_sim/%s_%d.%s.log" % (output_dir, iss, asm, test_iteration, target))
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log = ("%s/%s_sim/%s_%d.%s.log" % (output_dir, iss, test_log_name, test_iteration, target))
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else:
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log = ("%s/%s_sim/%s.%s.log" % (output_dir, iss, asm, target))
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log = ("%s/%s_sim/%s.%s.log" % (output_dir, iss, test_log_name, target))
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log_list.append(log)
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base_cmd = parse_iss_yaml(iss, iss_yaml, isa, target, setting_dir, debug_cmd, priv, spike_params)
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cmd = get_iss_cmd(base_cmd, elf, target, log)
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@ -550,7 +551,7 @@ def run_elf(c_test, iss_yaml, isa, target, mabi, gcc_opts, iss_opts, output_dir,
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def run_c(c_test, iss_yaml, isa, target, mabi, gcc_opts, iss_opts, output_dir,
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setting_dir, debug_cmd, linker, priv, spike_params):
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setting_dir, debug_cmd, linker, priv, spike_params, test_name = None):
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"""Run a directed c test with ISS
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Args:
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@ -592,12 +593,13 @@ def run_c(c_test, iss_yaml, isa, target, mabi, gcc_opts, iss_opts, output_dir,
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elf2bin(elf, binary, debug_cmd)
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log_list = []
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# ISS simulation
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test_log_name = test_name or c
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for iss in iss_list:
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run_cmd("mkdir -p %s/%s_sim" % (output_dir, iss))
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if log_format == 1:
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log = ("%s/%s_sim/%s_%d.%s.log" % (output_dir, iss, c, test_iteration, target))
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log = ("%s/%s_sim/%s_%d.%s.log" % (output_dir, iss, test_log_name, test_iteration, target))
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else:
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log = ("%s/%s_sim/%s.%s.log" % (output_dir, iss, c, target))
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log = ("%s/%s_sim/%s.%s.log" % (output_dir, iss, test_log_name, target))
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log_list.append(log)
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base_cmd = parse_iss_yaml(iss, iss_yaml, isa, target, setting_dir, debug_cmd, priv, spike_params)
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cmd = get_iss_cmd(base_cmd, elf, target, log)
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@ -1284,7 +1286,7 @@ def main():
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elif os.path.isfile(path_asm_test):
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run_assembly(path_asm_test, args.iss_yaml, args.isa, args.target, args.mabi, gcc_opts,
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args.iss, output_dir, args.core_setting_dir, args.debug, args.linker,
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args.priv, args.spike_params)
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args.priv, args.spike_params, test_entry['test'])
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else:
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if not args.debug:
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logging.error('%s does not exist' % path_asm_test)
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@ -1314,7 +1316,7 @@ def main():
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elif os.path.isfile(path_c_test):
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run_c(path_c_test, args.iss_yaml, args.isa, args.target, args.mabi, gcc_opts,
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args.iss, output_dir, args.core_setting_dir, args.debug, args.linker,
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args.priv, args.spike_params)
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args.priv, args.spike_params, test_entry['test'])
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else:
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if not args.debug:
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logging.error('%s does not exist' % path_c_test)
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