UVM: Basic sequence and driver running

This commit is contained in:
Florian Zaruba 2017-03-19 02:45:25 +01:00
parent c03c732ece
commit 5d83929e85
7 changed files with 40 additions and 24 deletions

View file

@ -9,7 +9,7 @@ top_level = alu_tb
# path to agents
agents = tb/agents/fu_if/fu_if.sv tb/agents/fu_if/fu_if_agent_pkg.sv
# this list contains the standalone components
src = include/ariane_pkg.svh alu.sv tb/env/alu_env_pkg.sv tb/test/alu_lib_pkg.sv tb/alu_tb.sv
src = include/ariane_pkg.svh alu.sv tb/sequences/alu_sequence_pkg.sv tb/env/alu_env_pkg.sv tb/test/alu_lib_pkg.sv tb/alu_tb.sv
# Search here for include files (e.g.: non-standalone components)
incdir = ./includes

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@ -32,12 +32,12 @@ function void fu_if_agent::build_phase(uvm_phase phase);
`uvm_fatal("CONFIG_LOAD", "Cannot get() configuration apb_agent_config from uvm_config_db. Have you set() it?")
m_driver = fu_if_driver::type_id::create("m_driver", this);
m_sequencer = spi_sequencer::type_id::create("m_sequencer", this);
m_sequencer = fu_if_sequencer::type_id::create("m_sequencer", this);
endfunction : build_phase
function void fu_if_agent::connect_phase(uvm_phase phase);
m_driver.seq_item_port.connect(m_sequencer.seq_item_export);
//m_driver.seq_item_port.connect(m_sequencer.seq_item_export);
m_driver.m_cfg = m_cfg;
endfunction: connect_phase
endfunction: connect_phase

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@ -2,7 +2,7 @@
// Date: 12/21/2016
// Description: Driver of the memory interface
class fu_if_driver extends uvm_driver #(sequence_item);
class fu_if_driver extends uvm_driver #(fu_if_seq_item);
// UVM Factory Registration Macro
`uvm_component_utils(fu_if_driver)
@ -28,21 +28,21 @@ function fu_if_driver::new(string name = "fu_if_driver", uvm_component parent =
endfunction
task fu_if_driver::run_phase(uvm_phase phase);
sequence_item cmd;
fu_if_seq_item cmd;
forever begin : cmd_loop
shortint unsigned result;
seq_item_port.get_next_item(cmd);
// using clocking blocks this is possible
@(fu.mck)
fu.mclk.operandA <= cmd.operandA;
fu.mclk.operandB <= cmd.operandB;
fu.mclk.operandC <= cmd.operandC;
fu.mclk.operator <= cmd.operator;
@(posedge fu.sck)
fu.sck.operand_a <= cmd.operand_a;
fu.sck.operand_b <= cmd.operand_b;
fu.sck.operand_c <= cmd.operand_c;
fu.sck.operator <= cmd.operator;
cmd.result <= fu.mclk.result;
cmd.compare_result <= fu.mclk.compare_result;
cmd.result = fu.result;
cmd.compare_result = fu.comparison_result;
seq_item_port.item_done();
@ -52,4 +52,4 @@ endtask : run_phase
function void fu_if_driver::build_phase(uvm_phase phase);
if (!uvm_config_db #(fu_if_agent_config)::get(this, "", "fu_if_agent_config", m_cfg) )
`uvm_fatal("CONFIG_LOAD", "Cannot get() configuration fu_if_agent_config from uvm_config_db. Have you set() it?")
endfunction: build_phase
endfunction: build_phase

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@ -0,0 +1,10 @@
package alu_sequence_pkg;
import fu_if_agent_pkg::*;
import uvm_pkg::*;
`include "uvm_macros.svh"
`include "fibonacci_sequence.svh"
endpackage

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@ -1,4 +1,5 @@
class fibonacci_sequence extends uvm_sequence #(sequence_item);
class fibonacci_sequence extends fu_if_seq;
`uvm_object_utils(fibonacci_sequence);
function new(string name = "fibonacci");
@ -9,7 +10,7 @@ class fibonacci_sequence extends uvm_sequence #(sequence_item);
task body();
byte unsigned n_minus_2=0;
byte unsigned n_minus_1=1;
sequence_item command;
fu_if_seq_item command;
command = fu_if_seq_item::type_id::create("command");
@ -17,9 +18,9 @@ class fibonacci_sequence extends uvm_sequence #(sequence_item);
`uvm_info("FIBONACCI", " Fib(02) = 01", UVM_MEDIUM);
for(int ff = 3; ff<=14; ff++) begin
start_item(command);
command.operandA = n_minus_2;
command.operandB = n_minus_1;
command.op = 7'b00;
command.operand_a = n_minus_2;
command.operand_b = n_minus_1;
command.operator = 7'b00;
finish_item(command);
@ -30,4 +31,4 @@ class fibonacci_sequence extends uvm_sequence #(sequence_item);
UVM_MEDIUM);
end
endtask : body
endclass : fibonacci_sequence
endclass : fibonacci_sequence

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@ -8,6 +8,8 @@ package alu_lib_pkg;
// Import the memory interface agent
import fu_if_agent_pkg::*;
import alu_env_pkg::*;
import alu_sequence_pkg::*;
// Test based includes like base test class and specializations of it
// ----------------
// Base test class
@ -18,4 +20,5 @@ package alu_lib_pkg;
// -------------------
// plain randomized test
`include "alu_test.svh"
endpackage
endpackage

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@ -28,9 +28,11 @@ endfunction
task alu_test::run_phase(uvm_phase phase);
phase.raise_objection(this, "alu_test");
fibonacci_sequence fibonacci_seq = fibonacci_sequence::type_id::create("fibonacci_sequence");
fibonacci_seq.start(m_env.m_fu_if_sequencer);
//fibonacci_sequence fibonacci_seq = fibonacci_sequence::type_id::create("fibonacci_sequence");
////fibonacci_seq.start(m_env.m_fu_if_sequencer);
// Testlogic goes here
#100ns;
phase.drop_objection(this, "alu_test");
endtask
endtask