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Move AXI Id widths to SoC package

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This commit is contained in:
Florian Zaruba 2019-03-15 18:25:31 +01:00
parent ad223cfd9f
commit 5eed9ef91d
3 changed files with 20 additions and 20 deletions
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8
include/ariane_axi_pkg.sv
View file

@ -20,17 +20,13 @@ package ariane_axi;
// used in axi_adapter.sv
typedef enum logic { SINGLE_REQ, CACHE_LINE_REQ } ad_req_t;
// 4 is recommended by AXI standard, so lets stick to it, do not change
localparam IdWidth = 4;
localparam IdWidthSlave = IdWidth + $clog2(ariane_soc::NrSlaves);
localparam UserWidth = 1;
localparam AddrWidth = 64;
localparam DataWidth = 64;
localparam StrbWidth = DataWidth / 8;
typedef logic [IdWidth-1:0] id_t;
typedef logic [IdWidth-1:0] id_slv_t;
typedef logic [ariane_soc::IdWidth-1:0] id_t;
typedef logic [ariane_soc::IdWidthSlave-1:0] id_slv_t;
typedef logic [AddrWidth-1:0] addr_t;
typedef logic [DataWidth-1:0] data_t;
typedef logic [StrbWidth-1:0] strb_t;

4
tb/ariane_soc_pkg.sv
View file

@ -19,6 +19,10 @@ package ariane_soc;
localparam ParameterBitwidth = PLICIdWidth;
localparam NrSlaves = 2; // actually masters, but slaves on the crossbar
// 4 is recommended by AXI standard, so lets stick to it, do not change
localparam IdWidth = 4;
localparam IdWidthSlave = IdWidth + $clog2(NrSlaves);
typedef enum int unsigned {
DRAM = 0,
GPIO = 1,

28
tb/ariane_testharness.sv
View file

@ -72,14 +72,14 @@ module ariane_testharness #(
AXI_BUS #(
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_ID_WIDTH ( ariane_axi::IdWidth ),
.AXI_ID_WIDTH ( ariane_soc::IdWidth ),
.AXI_USER_WIDTH ( AXI_USER_WIDTH )
) slave[ariane_soc::NrSlaves-1:0]();
AXI_BUS #(
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_ID_WIDTH ( ariane_axi::IdWidthSlave ),
.AXI_ID_WIDTH ( ariane_soc::IdWidthSlave ),
.AXI_USER_WIDTH ( AXI_USER_WIDTH )
) master[ariane_soc::NB_PERIPHERALS-1:0]();
@ -226,7 +226,7 @@ module ariane_testharness #(
);
axi2mem #(
.AXI_ID_WIDTH ( ariane_axi::IdWidthSlave ),
.AXI_ID_WIDTH ( ariane_soc::IdWidthSlave ),
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_USER_WIDTH ( AXI_USER_WIDTH )
@ -281,7 +281,7 @@ module ariane_testharness #(
logic [AXI_DATA_WIDTH-1:0] rom_rdata;
axi2mem #(
.AXI_ID_WIDTH ( ariane_axi::IdWidthSlave ),
.AXI_ID_WIDTH ( ariane_soc::IdWidthSlave ),
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_USER_WIDTH ( AXI_USER_WIDTH )
@ -310,7 +310,7 @@ module ariane_testharness #(
AXI_BUS #(
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_ID_WIDTH ( ariane_axi::IdWidthSlave ),
.AXI_ID_WIDTH ( ariane_soc::IdWidthSlave ),
.AXI_USER_WIDTH ( AXI_USER_WIDTH )
) dram();
@ -324,7 +324,7 @@ module ariane_testharness #(
axi_riscv_atomics_wrap #(
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_ID_WIDTH ( ariane_axi::IdWidthSlave ),
.AXI_ID_WIDTH ( ariane_soc::IdWidthSlave ),
.AXI_USER_WIDTH ( AXI_USER_WIDTH ),
.AXI_MAX_WRITE_TXNS ( 1 ),
.RISCV_WORD_WIDTH ( 64 )
@ -338,7 +338,7 @@ module ariane_testharness #(
AXI_BUS #(
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_ID_WIDTH ( ariane_axi::IdWidthSlave ),
.AXI_ID_WIDTH ( ariane_soc::IdWidthSlave ),
.AXI_USER_WIDTH ( AXI_USER_WIDTH )
) dram_delayed();
@ -474,7 +474,7 @@ module ariane_testharness #(
assign dram.b_user = '0;
axi2mem #(
.AXI_ID_WIDTH ( ariane_axi::IdWidthSlave ),
.AXI_ID_WIDTH ( ariane_soc::IdWidthSlave ),
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_USER_WIDTH ( AXI_USER_WIDTH )
@ -514,7 +514,7 @@ module ariane_testharness #(
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_USER_WIDTH ( AXI_USER_WIDTH ),
.AXI_ID_WIDTH ( ariane_axi::IdWidth )
.AXI_ID_WIDTH ( ariane_soc::IdWidth )
// .MASTER_SLICE_DEPTH ( 0 ),
// .SLAVE_SLICE_DEPTH ( 0 )
) i_axi_xbar (
@ -560,7 +560,7 @@ module ariane_testharness #(
clint #(
.AXI_ADDR_WIDTH ( AXI_ADDRESS_WIDTH ),
.AXI_DATA_WIDTH ( AXI_DATA_WIDTH ),
.AXI_ID_WIDTH ( ariane_axi::IdWidthSlave ),
.AXI_ID_WIDTH ( ariane_soc::IdWidthSlave ),
.NR_CORES ( 1 )
) i_clint (
.clk_i ( clk_i ),
@ -588,7 +588,7 @@ module ariane_testharness #(
ariane_peripherals #(
.AxiAddrWidth ( AXI_ADDRESS_WIDTH ),
.AxiDataWidth ( AXI_DATA_WIDTH ),
.AxiIdWidth ( ariane_axi::IdWidthSlave ),
.AxiIdWidth ( ariane_soc::IdWidthSlave ),
`ifndef VERILATOR
// disable UART when using Spike, as we need to rely on the mockuart
`ifdef SPIKE_TANDEM
@ -637,7 +637,7 @@ module ariane_testharness #(
ariane_axi::resp_t axi_ariane_resp;
ariane #(
.AxiIdWidth ( ariane_axi::IdWidth ),
.AxiIdWidth ( ariane_soc::IdWidth ),
.SwapEndianess ( 0 ),
.CachedAddrBeg ( ariane_soc::DRAMBase ),
.CachedAddrEnd ( (ariane_soc::DRAMBase + ariane_soc::DRAMLength) ),
@ -688,8 +688,8 @@ module ariane_testharness #(
// to use it
Axi4PC #(
.DATA_WIDTH(ariane_axi::DataWidth),
.WID_WIDTH(ariane_axi::IdWidthSlave),
.RID_WIDTH(ariane_axi::IdWidthSlave),
.WID_WIDTH(ariane_soc::IdWidthSlave),
.RID_WIDTH(ariane_soc::IdWidthSlave),
.AWUSER_WIDTH(ariane_axi::UserWidth),
.WUSER_WIDTH(ariane_axi::UserWidth),
.BUSER_WIDTH(ariane_axi::UserWidth),