remove round interval (#2353)

.gitlab-ci/expected_synth.yml

@@ -1,2 +1,2 @@
 cv32a65x:
-  gates: 162333
+  gates: 162197

Bender.yml

@@ -110,7 +110,6 @@ sources:
       - core/ariane_regfile_ff.sv
       - core/ariane_regfile_fpga.sv
       - core/scoreboard.sv
-      - core/round_interval.sv
       - core/store_buffer.sv
       - core/amo_buffer.sv
       - core/store_unit.sv

Flist.ariane

@@ -94,7 +94,6 @@ core/mmu_sv39x4/ptw_sv39x4.sv
 core/ariane_regfile_ff.sv
 core/re_name.sv
 core/scoreboard.sv
-core/round_interval.sv
 core/store_buffer.sv
 core/amo_buffer.sv
 core/store_unit.sv

core/Flist.cva6

@@ -126,7 +126,6 @@ ${CVA6_REPO_DIR}/core/ariane_regfile_ff.sv
 ${CVA6_REPO_DIR}/core/ariane_regfile_fpga.sv
 // NOTE: scoreboard.sv modified for DSIM (unchanged for other simulators)
 ${CVA6_REPO_DIR}/core/scoreboard.sv
-${CVA6_REPO_DIR}/core/round_interval.sv
 ${CVA6_REPO_DIR}/core/store_buffer.sv
 ${CVA6_REPO_DIR}/core/amo_buffer.sv
 ${CVA6_REPO_DIR}/core/store_unit.sv

core/round_interval.sv

@@ -1,53 +0,0 @@
-// Copyright 2024 Thales Silicon Security
-//
-// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
-// You may obtain a copy of the License at https://solderpad.org/licenses/
-//
-// Original Author: Côme ALLART - Thales
-
-module round_interval #(
-    parameter int unsigned S = 1,
-    parameter int unsigned L = 1 << S
-) (
-    // Start index
-    // Included in the interval
-    input logic [S-1:0] start_i,
-    // Stop index
-    // Not included in the interval
-    input logic [S-1:0] stop_i,
-
-    // The interval from start to stop, rounding
-    // Considered full when start_i == stop_i
-    output logic [L-1:0] active_o
-);
-
-  // Bit high at index start/stop
-  logic [L-1:0] a;
-  logic [L-1:0] b;
-
-  for (genvar i = 0; i < L; i++) begin
-    assign a[i] = start_i == i;
-    assign b[i] = stop_i == i;
-  end
-
-  // Propagation to the higher indexes: >=
-  logic [L-1:0] ge_a;
-  logic [L-1:0] ge_b;
-
-  assign ge_b[0] = b[0];
-  assign ge_a[0] = a[0];
-  for (genvar i = 1; i < L; i++) begin
-    assign ge_b[i] = ge_b[i-1] || b[i];
-    assign ge_a[i] = ge_a[i-1] || a[i];
-  end
-
-  // < is the negation of >=
-  logic [L-1:0] lt_b;
-  assign lt_b = ~ge_b;
-
-  // Build the interval
-  assign active_o = (start_i <= stop_i) ? lt_b & ge_a : lt_b | ge_a;
-
-endmodule

core/scoreboard.sv

@@ -242,10 +242,8 @@ module scoreboard #(
     // ------------
     if (CVA6Cfg.SpeculativeSb) begin
       if (bmiss) begin
-        for (int unsigned i = 0; i < CVA6Cfg.NR_SB_ENTRIES; i++) begin
-          if (speculative_instrs[i]) begin
-            mem_n[i].cancelled = 1'b1;
-          end
+        if (after_flu_wb != issue_pointer[0]) begin
+          mem_n[after_flu_wb].cancelled = 1'b1;
         end
       end
     end
@@ -280,16 +278,6 @@ module scoreboard #(
   assign bmiss = resolved_branch_i.valid && resolved_branch_i.is_mispredict;
   assign after_flu_wb = trans_id_i[ariane_pkg::FLU_WB] + 'd1;
 
-  if (CVA6Cfg.SpeculativeSb) begin : find_speculative_instrs
-    round_interval #(
-        .S(CVA6Cfg.TRANS_ID_BITS)
-    ) i_speculative_instrs (
-        .start_i (after_flu_wb),
-        .stop_i  (issue_pointer_q),
-        .active_o(speculative_instrs)
-    );
-  end
-
   // FIFO counter updates
   if (CVA6Cfg.NrCommitPorts == 2) begin : gen_commit_ports
     assign num_commit = commit_ack_i[1] + commit_ack_i[0];