Fix signaling issue in rgmii converter

CHANGELOG.md

@@ -10,18 +10,21 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 
 ### Added
 
-- Commit log feature
-- Support for A-Extension
+- Preliminary support for A-Extension
 - Preliminary FP support
 - Preliminary support for OpenPiton cache system
+- Commit log feature
 - Provisioned `aw_top` signal for close to memory atomics
 - FPGA Support
 - Misc bug-fixes
+- Platform Level Interrupt Controller (PLIC)
+- FPGA Bootrom with capability to boot from SD Card
 
 ### Changed
 
-- core_id / cluster_id inputs have been merged to hard_id input
-- Three AXI ports have been merged into one
+- core_id / cluster_id inputs have been merged to hard_id input (interface changes)
+- The three AXI ports have been merged into one (interface changes)
+- [Bugfix] Wrong flagging of memory in machine mode if high bits (63-38) are not equal #136
 
 ### 3.0.0
 

fpga/constraints/genesys-2.xdc

@@ -78,7 +78,11 @@ set_input_delay -clock [get_clocks eth_rxck_virt] -min -add_delay 0.000 [get_por
 set_input_delay -clock [get_clocks eth_rxck_virt] -max -add_delay 4.000 [get_ports eth_rxctl]
 
 # Output Constraints
-create_generated_clock -name eth_txck -source [get_pins i_ariane_peripherals/gen_ethernet.i_rgmii_to_mii_conv_xilinx/net_phy_txc_oddr/C] -divide_by 1 -invert [get_ports eth_txck]
+create_generated_clock -name eth_txck -source [get_pins i_ariane_peripherals/gen_ethernet.i_rgmii_to_mii_conv_xilinx/net_phy_txc_oddr/C] -multiply_by 1 [get_ports eth_txck]
+
+# Constraint RGMII interface
+set_output_delay -clock eth_txck 2.000 [get_ports eth_txctl]
+set_output_delay -clock eth_txck 2.000 [get_ports {eth_txd[*]}]
 
 ## SD Card
 set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS33} [get_ports spi_clk_o]

fpga/src/ariane_peripherals_xilinx.sv

@@ -757,6 +757,9 @@ module ariane_peripherals #(
             .phy_mdc       ( phy_mdc                )
         );
 
+        assign phy_crs = 1'b0;
+        assign phy_col = 1'b0;
+
         rgmii_to_mii_conv_xilinx i_rgmii_to_mii_conv_xilinx (
             .rgmii_phy_txc   ( eth_txck     ),
             .rgmii_phy_txctl ( eth_txctl    ),

fpga/src/ariane_xilinx.sv

@@ -31,11 +31,11 @@ module ariane_xilinx (
   output logic [ 0:0]  ddr3_cs_n   ,
   output logic [ 3:0]  ddr3_dm     ,
   output logic [ 0:0]  ddr3_odt    ,
-  output wire          eth_txck    ,
+  output wire          eth_rst_n   ,
   input  wire          eth_rxck    ,
   input  wire          eth_rxctl   ,
   input  wire [3:0]    eth_rxd     ,
-  output wire          eth_rst_n   ,
+  output wire          eth_txck    ,
   output wire          eth_txctl   ,
   output wire [3:0]    eth_txd     ,
   inout  wire          eth_mdio    ,

fpga/src/rgmii_to_mii_conv_xilinx.sv

@@ -58,14 +58,21 @@ module rgmii_to_mii_conv_xilinx (
     // -------------
     IOBUF mdio_io_iobuf (.I (net_mdio_i), .IO(rgmii_phy_mdio), .O (net_mdio_o), .T (net_mdio_t));
     assign rgmii_phy_mdc = net_phy_mdc;
+    assign rgmii_phy_rst_n = net_phy_rst_n;
 
     // -------------
     // TX
     // -------------
+    // net_phy_tx_clk:  ___|------|______|------|______|------|______|
+    // rgmii_phy_txc:   ---|______|------|______|------|______|------|
+    // net_phy_tx_en:   -----_________________________________________
+    // rgmii_phy_txctl: _____--------------___________________________
+
+    // basically inverts the clock
     ODDR net_phy_txc_oddr (
-        .Q  ( rgmii_phy_txc     ), // 1-bit DDR output (ODDR register output)
         .C  ( net_phy_tx_clk    ), // 1-bit clock input (The CLK pin represents the clock input pin)
         .CE ( 1'b1              ), // 1-bit clock enable input (CE represents the clock enable pin. When asserted Low,
+        .Q  ( rgmii_phy_txc     ), // 1-bit DDR output (ODDR register output)
                                    // this port disables the output clock on port Q.)
         .D1 ( 1'b0              ), // 1-bit data input (positive edge) (ODDR register inputs)
         .D2 ( 1'b1              ), // 1-bit data input (negative edge) (ODDR register inputs)
@@ -77,16 +84,16 @@ module rgmii_to_mii_conv_xilinx (
 
     // D-FF
     FD net_phy_txctl_dff (
-        .Q ( rgmii_phy_txctl ),
+        .C ( net_phy_tx_clk  ),
         .D ( net_phy_tx_en   ),
-        .C ( net_phy_tx_clk  )
+        .Q ( rgmii_phy_txctl )
     );
 
     for (genvar i = 0; i < 4; i++) begin : gen_net_phy_txd
         FD net_phy_txd_dff (
-            .Q ( rgmii_phy_txd[i]   ),
+            .C ( net_phy_tx_clk     ),
             .D ( net_phy_tx_data[i] ),
-            .C ( net_phy_tx_clk     )
+            .Q ( rgmii_phy_txd[i]   )
         );
     end
 
@@ -143,27 +150,43 @@ module rgmii_to_mii_conv_xilinx (
     );
 
     BUFG BUFG_inst (
-      .O ( net_phy_rx_clk   ),
-      .I ( net_phy_rxc_delayed )
+      .I ( net_phy_rxc_delayed ),
+      .O ( net_phy_rx_clk      ),
     );
 
-    always @(posedge net_phy_rx_clk) begin
+    // The RX_CTL signal carries RXDV (data valid) on the rising edge, and (RXDV xor RXER)
+    // on the falling edge.
+    // data valid is transmitted on positive edge
+    always_ff @(posedge net_phy_rx_clk) begin
         if (~rgmii_phy_rst_n) begin
-            net_phy_rx_dv_f   <= 1'b0;
-            net_phy_rx_err_f  <= 1'b0;
-            net_phy_rx_dv_ff  <= 1'b0;
-            net_phy_rx_err_ff <= 1'b0;
+            net_phy_rx_dv_f <= 1'b0;
         end else begin
-            net_phy_rx_dv_f   <= rgmii_phy_rxctl;
-            net_phy_rx_err_f  <= rgmii_phy_rxctl;
-            net_phy_rxd_f     <= rgmii_phy_rxd;
-            net_phy_rx_dv_ff  <= net_phy_rx_dv_f;
-            net_phy_rx_err_ff <= net_phy_rx_err_f;
-            net_phy_rxd_ff    <= net_phy_rxd_f;
+            net_phy_rx_dv_f <= rgmii_phy_rxctl;
         end
     end
 
-    assign rgmii_phy_rst_n = net_phy_rst_n;
+    // data error is encoded on negative edge of rxctl
+    always_ff @(negedge net_phy_rx_clk) begin
+        if (~rgmii_phy_rst_n) begin
+            net_phy_rx_err_f <= 1'b0;
+        end else begin
+            net_phy_rx_err_f <= rgmii_phy_rxctl;
+        end
+    end
+
+    always_ff @(posedge net_phy_rx_clk) begin
+        if (~rgmii_phy_rst_n) begin
+            net_phy_rxd_f     <= '0;
+            net_phy_rxd_ff    <= '0;
+            net_phy_rx_dv_ff  <= 1'b0;
+            net_phy_rx_err_ff <= 1'b0;
+        end else begin
+            net_phy_rxd_f     <= rgmii_phy_rxd;
+            net_phy_rxd_ff    <= net_phy_rxd_f;
+            net_phy_rx_dv_ff  <= net_phy_rx_dv_f;
+            net_phy_rx_err_ff <= net_phy_rx_err_f;
+        end
+    end
 
     assign net_phy_dv = net_phy_rx_dv_ff;
     assign net_phy_rx_er = net_phy_rx_dv_ff ^ net_phy_rx_err_ff;