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https://github.com/openhwgroup/cva6.git
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🎨 Tidy up FPU wrapper
This commit is contained in:
Stefan Mach
Florian Zaruba
parent
a4e49fc872
commit
60724973a7
1 changed files with 62 additions and 63 deletions
125
src/fpu_wrap.sv
125
src/fpu_wrap.sv
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@ -136,18 +136,18 @@ generate
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// Formats
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unique case (fpu_fmt_i)
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// FP32
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2'b00 : fpu_dstfmt_d = fpnew_pkg::FP32;
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2'b00: fpu_dstfmt_d = fpnew_pkg::FP32;
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// FP64 or FP16ALT (vectorial)
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2'b01 : fpu_dstfmt_d = fpu_vec_op_d ? fpnew_pkg::FP16ALT : fpnew_pkg::FP64;
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2'b01: fpu_dstfmt_d = fpu_vec_op_d ? fpnew_pkg::FP16ALT : fpnew_pkg::FP64;
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// FP16 or FP16ALT (scalar)
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2'b10 : begin
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2'b10: begin
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if (!fpu_vec_op_d && fpu_rm_i==3'b101)
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fpu_dstfmt_d = fpnew_pkg::FP16ALT;
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else
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fpu_dstfmt_d = fpnew_pkg::FP16;
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end
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// FP8
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default : fpu_dstfmt_d = fpnew_pkg::FP8;
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default: fpu_dstfmt_d = fpnew_pkg::FP8;
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endcase
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// By default, set src=dst
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@ -156,54 +156,54 @@ generate
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// Operations (this can modify the rounding mode field and format!)
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unique case (fu_data_i.operator)
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// Addition
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FADD : begin
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FADD: begin
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fpu_op_d = fpnew_pkg::ADD;
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replicate_c = 1'b1; // second operand is in C
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end
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// Subtraction is modified ADD
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FSUB : begin
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FSUB: begin
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fpu_op_d = fpnew_pkg::ADD;
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fpu_op_mod_d = 1'b1;
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replicate_c = 1'b1; // second operand is in C
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end
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// Multiplication
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FMUL : fpu_op_d = fpnew_pkg::MUL;
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FMUL: fpu_op_d = fpnew_pkg::MUL;
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// Division
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FDIV : fpu_op_d = fpnew_pkg::DIV;
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FDIV: fpu_op_d = fpnew_pkg::DIV;
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// Min/Max - OP is encoded in rm (000-001)
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FMIN_MAX : begin
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FMIN_MAX: begin
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fpu_op_d = fpnew_pkg::MINMAX;
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fpu_rm_d = {1'b0, fpu_rm_i[1:0]}; // mask out AH encoding bit
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check_ah = 1'b1; // AH has RM MSB encoding
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end
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// Square Root
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FSQRT : fpu_op_d = fpnew_pkg::SQRT;
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FSQRT: fpu_op_d = fpnew_pkg::SQRT;
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// Fused Multiply Add
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FMADD : fpu_op_d = fpnew_pkg::FMADD;
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FMADD: fpu_op_d = fpnew_pkg::FMADD;
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// Fused Multiply Subtract is modified FMADD
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FMSUB : begin
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FMSUB: begin
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fpu_op_d = fpnew_pkg::FMADD;
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fpu_op_mod_d = 1'b1;
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end
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// Fused Negated Multiply Subtract
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FNMSUB : fpu_op_d = fpnew_pkg::FNMSUB;
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FNMSUB: fpu_op_d = fpnew_pkg::FNMSUB;
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// Fused Negated Multiply Add is modified FNMSUB
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FNMADD : begin
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FNMADD: begin
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fpu_op_d = fpnew_pkg::FNMSUB;
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fpu_op_mod_d = 1'b1;
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end
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// Float to Int Cast - Op encoded in lowest two imm bits or rm
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FCVT_F2I : begin
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FCVT_F2I: begin
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fpu_op_d = fpnew_pkg::F2I;
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// Vectorial Ops encoded in R bit
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if (fpu_vec_op_d) begin
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fpu_op_mod_d = fpu_rm_i[0];
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vec_replication = 1'b0; // no replication, R bit used for op
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unique case (fpu_fmt_i)
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2'b00 : fpu_ifmt_d = fpnew_pkg::INT32;
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2'b00: fpu_ifmt_d = fpnew_pkg::INT32;
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2'b01,
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2'b10 : fpu_ifmt_d = fpnew_pkg::INT16;
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2'b11 : fpu_ifmt_d = fpnew_pkg::INT8;
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2'b10: fpu_ifmt_d = fpnew_pkg::INT16;
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2'b11: fpu_ifmt_d = fpnew_pkg::INT8;
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endcase
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// Scalar casts encoded in imm
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end else begin
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@ -215,17 +215,17 @@ generate
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end
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end
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// Int to Float Cast - Op encoded in lowest two imm bits or rm
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FCVT_I2F : begin
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FCVT_I2F: begin
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fpu_op_d = fpnew_pkg::I2F;
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// Vectorial Ops encoded in R bit
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if (fpu_vec_op_d) begin
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fpu_op_mod_d = fpu_rm_i[0];
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vec_replication = 1'b0; // no replication, R bit used for op
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unique case (fpu_fmt_i)
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2'b00 : fpu_ifmt_d = fpnew_pkg::INT32;
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2'b00: fpu_ifmt_d = fpnew_pkg::INT32;
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2'b01,
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2'b10 : fpu_ifmt_d = fpnew_pkg::INT16;
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2'b11 : fpu_ifmt_d = fpnew_pkg::INT8;
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2'b10: fpu_ifmt_d = fpnew_pkg::INT16;
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2'b11: fpu_ifmt_d = fpnew_pkg::INT8;
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endcase
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// Scalar casts encoded in imm
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end else begin
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@ -237,7 +237,7 @@ generate
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end
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end
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// Float to Float Cast - Source format encoded in lowest two/three imm bits
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FCVT_F2F : begin
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FCVT_F2F: begin
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fpu_op_d = fpnew_pkg::F2F;
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// Vectorial ops encoded in lowest two imm bits
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if (fpu_vec_op_d) begin
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@ -260,13 +260,13 @@ generate
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end
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end
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// Scalar Sign Injection - op encoded in rm (000-010)
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FSGNJ : begin
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FSGNJ: begin
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fpu_op_d = fpnew_pkg::SGNJ;
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fpu_rm_d = {1'b0, fpu_rm_i[1:0]}; // mask out AH encoding bit
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check_ah = 1'b1; // AH has RM MSB encoding
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end
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// Move from FPR to GPR - mapped to SGNJ-passthrough since no recoding
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FMV_F2X : begin
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FMV_F2X: begin
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fpu_op_d = fpnew_pkg::SGNJ;
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fpu_rm_d = 3'b011; // passthrough without checking nan-box
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fpu_op_mod_d = 1'b1; // no NaN-Boxing
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@ -274,113 +274,112 @@ generate
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vec_replication = 1'b0; // no replication, we set second operand
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end
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// Move from GPR to FPR - mapped to NOP since no recoding
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FMV_X2F : begin
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FMV_X2F: begin
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fpu_op_d = fpnew_pkg::SGNJ;
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fpu_rm_d = 3'b011; // passthrough without checking nan-box
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check_ah = 1'b1; // AH has RM MSB encoding
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vec_replication = 1'b0; // no replication, we set second operand
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end
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// Scalar Comparisons - op encoded in rm (000-010)
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FCMP : begin
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FCMP: begin
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fpu_op_d = fpnew_pkg::CMP;
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fpu_rm_d = {1'b0, fpu_rm_i[1:0]}; // mask out AH encoding bit
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check_ah = 1'b1; // AH has RM MSB encoding
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end
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// Classification
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FCLASS : begin
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FCLASS: begin
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fpu_op_d = fpnew_pkg::CLASSIFY;
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fpu_rm_d = {1'b0, fpu_rm_i[1:0]}; // mask out AH encoding bit - CLASS doesn't care anyways
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check_ah = 1'b1; // AH has RM MSB encoding
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end
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// Vectorial Minimum - set up scalar encoding in rm
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VFMIN : begin
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VFMIN: begin
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fpu_op_d = fpnew_pkg::MINMAX;
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fpu_rm_d = 3'b000; // min
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end
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// Vectorial Maximum - set up scalar encoding in rm
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VFMAX : begin
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VFMAX: begin
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fpu_op_d = fpnew_pkg::MINMAX;
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fpu_rm_d = 3'b001; // max
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end
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// Vectorial Sign Injection - set up scalar encoding in rm
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VFSGNJ : begin
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VFSGNJ: begin
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fpu_op_d = fpnew_pkg::SGNJ;
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fpu_rm_d = 3'b000; // sgnj
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end
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// Vectorial Negated Sign Injection - set up scalar encoding in rm
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VFSGNJN : begin
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VFSGNJN: begin
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fpu_op_d = fpnew_pkg::SGNJ;
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fpu_rm_d = 3'b001; // sgnjn
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end
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// Vectorial Xored Sign Injection - set up scalar encoding in rm
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VFSGNJX : begin
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VFSGNJX: begin
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fpu_op_d = fpnew_pkg::SGNJ;
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fpu_rm_d = 3'b010; // sgnjx
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end
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// Vectorial Equals - set up scalar encoding in rm
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VFEQ : begin
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VFEQ: begin
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fpu_op_d = fpnew_pkg::CMP;
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fpu_rm_d = 3'b010; // eq
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end
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// Vectorial Not Equals - set up scalar encoding in rm
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VFNE : begin
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VFNE: begin
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fpu_op_d = fpnew_pkg::CMP;
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fpu_op_mod_d = 1'b1; // invert output
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fpu_rm_d = 3'b010; // eq
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end
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// Vectorial Less Than - set up scalar encoding in rm
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VFLT : begin
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VFLT: begin
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fpu_op_d = fpnew_pkg::CMP;
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fpu_rm_d = 3'b001; // lt
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end
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// Vectorial Greater or Equal - set up scalar encoding in rm
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VFGE : begin
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VFGE: begin
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fpu_op_d = fpnew_pkg::CMP;
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fpu_op_mod_d = 1'b1; // invert output
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fpu_rm_d = 3'b001; // lt
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end
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// Vectorial Less or Equal - set up scalar encoding in rm
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VFLE : begin
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VFLE: begin
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fpu_op_d = fpnew_pkg::CMP;
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fpu_rm_d = 3'b000; // le
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end
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// Vectorial Greater Than - set up scalar encoding in rm
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VFGT : begin
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VFGT: begin
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fpu_op_d = fpnew_pkg::CMP;
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fpu_op_mod_d = 1'b1; // invert output
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fpu_rm_d = 3'b000; // le
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end
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// Vectorial Convert-and-Pack from FP32, lower 4 entries
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VFCPKAB_S : begin
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VFCPKAB_S: begin
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fpu_op_d = fpnew_pkg::CPKAB;
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fpu_op_mod_d = fpu_rm_i[0]; // A/B selection from R bit
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vec_replication = 1'b0; // no replication, R bit used for op
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fpu_srcfmt_d = fpnew_pkg::FP32; // Cast from FP32
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vec_replication = 1'b0; // no replication, R bit used for op
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fpu_srcfmt_d = fpnew_pkg::FP32; // Cast from FP32
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end
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// Vectorial Convert-and-Pack from FP32, upper 4 entries
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VFCPKCD_S : begin
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VFCPKCD_S: begin
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fpu_op_d = fpnew_pkg::CPKCD;
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fpu_op_mod_d = fpu_rm_i[0]; // C/D selection from R bit
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vec_replication = 1'b0; // no replication, R bit used for op
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fpu_srcfmt_d = fpnew_pkg::FP32; // Cast from FP32
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vec_replication = 1'b0; // no replication, R bit used for op
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fpu_srcfmt_d = fpnew_pkg::FP32; // Cast from FP32
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end
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// Vectorial Convert-and-Pack from FP64, lower 4 entries
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VFCPKAB_D : begin
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VFCPKAB_D: begin
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fpu_op_d = fpnew_pkg::CPKAB;
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fpu_op_mod_d = fpu_rm_i[0]; // A/B selection from R bit
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vec_replication = 1'b0; // no replication, R bit used for op
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fpu_srcfmt_d = fpnew_pkg::FP64; // Cast from FP64
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vec_replication = 1'b0; // no replication, R bit used for op
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fpu_srcfmt_d = fpnew_pkg::FP64; // Cast from FP64
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end
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// Vectorial Convert-and-Pack from FP64, upper 4 entries
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VFCPKCD_D : begin
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VFCPKCD_D: begin
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fpu_op_d = fpnew_pkg::CPKCD;
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fpu_op_mod_d = fpu_rm_i[0]; // C/D selection from R bit
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vec_replication = 1'b0; // no replication, R bit used for op
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fpu_srcfmt_d = fpnew_pkg::FP64; // Cast from FP64
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vec_replication = 1'b0; // no replication, R bit used for op
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fpu_srcfmt_d = fpnew_pkg::FP64; // Cast from FP64
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end
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// No changes per default
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default : ; //nothing
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default: ; //nothing
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endcase
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// Scalar AH encoding fixing
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@ -392,17 +391,17 @@ generate
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if (fpu_vec_op_d && vec_replication) begin
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if (replicate_c) begin
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unique case (fpu_dstfmt_d)
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fpnew_pkg::FP32 : operand_c_d = RVD ? {2{operand_c_i[31:0]}} : operand_c_i;
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fpnew_pkg::FP32: operand_c_d = RVD ? {2{operand_c_i[31:0]}} : operand_c_i;
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fpnew_pkg::FP16,
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fpnew_pkg::FP16ALT : operand_c_d = RVD ? {4{operand_c_i[15:0]}} : {2{operand_c_i[15:0]}};
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fpnew_pkg::FP8 : operand_c_d = RVD ? {8{operand_c_i[7:0]}} : {4{operand_c_i[7:0]}};
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fpnew_pkg::FP16ALT: operand_c_d = RVD ? {4{operand_c_i[15:0]}} : {2{operand_c_i[15:0]}};
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fpnew_pkg::FP8: operand_c_d = RVD ? {8{operand_c_i[7:0]}} : {4{operand_c_i[7:0]}};
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endcase // fpu_dstfmt_d
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end else begin
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unique case (fpu_dstfmt_d)
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fpnew_pkg::FP32 : operand_b_d = RVD ? {2{operand_b_i[31:0]}} : operand_b_i;
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fpnew_pkg::FP32: operand_b_d = RVD ? {2{operand_b_i[31:0]}} : operand_b_i;
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fpnew_pkg::FP16,
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fpnew_pkg::FP16ALT : operand_b_d = RVD ? {4{operand_b_i[15:0]}} : {2{operand_b_i[15:0]}};
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fpnew_pkg::FP8 : operand_b_d = RVD ? {8{operand_b_i[7:0]}} : {4{operand_b_i[7:0]}};
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fpnew_pkg::FP16ALT: operand_b_d = RVD ? {4{operand_b_i[15:0]}} : {2{operand_b_i[15:0]}};
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fpnew_pkg::FP8: operand_b_d = RVD ? {8{operand_b_i[7:0]}} : {4{operand_b_i[7:0]}};
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endcase // fpu_dstfmt_d
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end
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end
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@ -424,7 +423,7 @@ generate
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// FSM
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unique case (state_q)
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// Default state, ready for instructions
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READY : begin
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READY: begin
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fpu_ready_o = 1'b1; // Act as if FPU ready
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fpu_in_valid = fpu_valid_i; // Forward input valid to FPU
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// There is a transaction but the FPU can't handle it
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@ -435,7 +434,7 @@ generate
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end
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end
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// We're stalling the upstream (ready=0)
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STALL : begin
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STALL: begin
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fpu_in_valid = 1'b1; // we have data for the FPU
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use_hold = 1'b1; // the data comes from the hold reg
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// Wait until it's consumed
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@ -445,12 +444,12 @@ generate
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end
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end
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// Default: emit default values
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default : ;
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default: ;
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endcase
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// Flushing will override issue and go back to idle
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if (flush_i) begin
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state_d = READY;
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state_d = READY;
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end
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end
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