Merge pull request #2084 from ThalesSiliconSecurity/gcc13

Add GCC version check and README to build GCC.

cva6/README.md

@@ -19,13 +19,25 @@ There are README files in each directory with additional information.
 ## Prerequisites
 To execute tests on CVA6 core, you need a RISC-V toolchain.
 
-For instance, you can use the gcc 10 toolchain.
-To build and install it, use scripts located at
-https://github.com/ThalesGroup/cva6-tools
+Be aware that only gcc 11.1.0 or newer are supported in core-v-verif repository.
+To build and install riscv gcc compiler in local, you can use the following commands :
 
-Once the toolchain is installed, set the `RISCV` environment variable
-to your toolchain installation path e.g. `RISCV = /path/to/gcc-10.2`
-to run the test scripts.
+- `git clone https://github.com/riscv-collab/riscv-gnu-toolchain`
+- `cd riscv-gnu-toolchain`
+- `git clone https://github.com/gcc-mirror/gcc -b releases/gcc-13 gcc-13`
+- ```./configure –prefix:/path/to/installation/directory --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" --with-gcc-src=`pwd`/gcc-13```
+- `make –j32`
+
+These commands will install the riscv gcc 13.1.0 compiler which is the latest version.
+Once running the previous commands, your environment must be updated with :
+
+- `export RISCV=/path/to/installation/directory`
+- `export RISCV_PREFIX=/path/to/installation/directory/bin/riscv64-unknown-`
+- `export RISCV_GCC=/path/to/installation/directory/bin/riscv64-unknown-gcc`
+- `export CV_SW_PREFIX=riscv64-unknown-elf-`
+
+This 4 variables will ensure you use correctly the new gcc compiler you have just installed.
+You will now be able to run the test scripts.
 
 ## Test execution
 Run one of the shell scripts:

cva6/regress/dv-generated-tests.sh

@@ -104,7 +104,7 @@ printf "+=======================================================================
 j=0
 while [[ $j -lt ${#TEST_NAME[@]} ]];do
   cp ../env/corev-dv/custom/riscv_custom_instr_enum.sv ./dv/src/isa/custom/
-  python3 cva6.py --testlist=$TESTLIST_FILE --test ${TEST_NAME[j]} --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imac/ --mabi ilp32 --isa rv32imac --simulator_yaml ../env/corev-dv/simulator.yaml --iss=vcs-uvm,spike -i ${I[j]} -bz 1 --iss_timeout 300 --isa_extension=zicsr,zifencei
+  python3 cva6.py --testlist=$TESTLIST_FILE --test ${TEST_NAME[j]} --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imac/ --mabi ilp32 --isa rv32imac --simulator_yaml ../env/corev-dv/simulator.yaml --iss=vcs-uvm,spike -i ${I[j]} -bz 1 --iss_timeout 300
   n=0
   echo "Generate the test : ${TEST_NAME[j]}"
 #this while loop detects the failed tests from the log file and remove them
@@ -128,6 +128,6 @@ j=0
 elif [[ "$list_num" = 0 ]];then
    printf "==== Execute Directed tests to improve functional coverage of isa, by hiting some corners !!! ====\n\n"
    printf "==== These tests are generated by RISCV-DV before modify to hit some specific values ====\n\n"
-   python3 cva6.py --testlist=$DIRECTED_TESTLIST --iss_yaml cva6.yaml --target $DV_TARGET --iss=vcs-uvm,spike --isa_extension=zicsr,zifencei
+   python3 cva6.py --testlist=$DIRECTED_TESTLIST --iss_yaml cva6.yaml --target $DV_TARGET --iss=vcs-uvm,spike
 fi
 cd -

cva6/regress/dv-riscv-compliance.sh

@@ -27,5 +27,5 @@ if ! [ -n "$DV_SIMULATORS" ]; then
 fi
 
 cd cva6/sim
-python3 cva6.py --testlist=../tests/testlist_riscv-compliance-$DV_TARGET.yaml --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS --isa_extension=zicsr,zifencei
+python3 cva6.py --testlist=../tests/testlist_riscv-compliance-$DV_TARGET.yaml --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS
 cd -

cva6/regress/dv-riscv-tests.sh

@@ -34,6 +34,6 @@ fi
 cd cva6/sim
 for TESTLIST in $DV_TESTLISTS
 do
-  python3 cva6.py --testlist=$TESTLIST --target $DV_TARGET --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml $DV_OPTS --isa_extension=zicsr,zifencei
+  python3 cva6.py --testlist=$TESTLIST --target $DV_TARGET --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml $DV_OPTS
 done
 cd -

cva6/sim/cva6.py

@@ -836,7 +836,7 @@ def setup_parser():
                       help="Run test N times with random seed")
   parser.add_argument("--sv_seed", type=str, default="1",
                       help="Run test with a specific seed")
-  parser.add_argument("--isa_extension", type=str, default="zicsr",
+  parser.add_argument("--isa_extension", type=str, default="",
                       help="Choose additional z, s, x extensions")
   return parser
 
@@ -852,8 +852,9 @@ def load_config(args, cwd):
   
   global isa_extension_list
   isa_extension_list = args.isa_extension.split(",")  
-  
-  
+  isa_extension_list.append("zicsr")
+  isa_extension_list.append("zifencei")
+
   if args.debug:
     args.debug = open(args.debug, "w")
   if not args.csr_yaml:
@@ -989,14 +990,22 @@ def main():
     os.environ["CVA6_DV_ROOT"]  = cwd + "/../env/corev-dv"
     setup_logging(args.verbose)
     logg = logging.getLogger()
+    #Check gcc version
+    gcc_path=get_env_var("RISCV_GCC")
+    version=run_cmd("%s --version" % gcc_path)
+    gcc_version=re.match(".*\s(\d+\.\d+\.\d+).*", version)
+    gcc_version=gcc_version.group(1)
+    version_number=gcc_version.split('.')
+    if int(version_number[0])<11 :
+      logging.error('Your are currently using version %s of gcc, please update your version to version 11.1.0 or more to use all features of this script' % gcc_version)
+      sys.exit(RET_FAIL)
     #print environment softwares
-    gcc_version=get_env_var("RISCV_GCC")
     logging.info("GCC Version : %s" % (gcc_version))
     spike_version=get_env_var("SPIKE_ROOT")
     logging.info("Spike Version : %s" % (spike_version))
     verilator_version=run_cmd("verilator --version")
     logging.info("Verilator Version : %s" % (verilator_version))
-    # create file handler which logs even debug messages
+    # create file handler which logs even debug messages13.1.1
     fh = logging.FileHandler('logfile.log')
     fh.setLevel(logging.DEBUG)
     # create formatter and add it to the handlers
@@ -1010,9 +1019,10 @@ def main():
     output_dir = create_output(args.o, args.noclean, cwd+"/out_")
     
     #add z,s,x extensions to the isa if there are some
-    if isa_extension_list !=['none']:
+    if isa_extension_list !=['']:	
       for i in isa_extension_list:
-        args.isa += (f"_{i}")
+        if i!= "":
+          args.isa += (f"_{i}")
         
     if args.verilog_style_check:
       logging.debug("Run style check")
@@ -1212,3 +1222,4 @@ if __name__ == "__main__":
   sys.path.append(os.getcwd()+"/../../core-v-cores/cva6")
   from config_pkg_generator import *
   main()
+