README caveat and hard coded paths (#2967)

A couple simple changes which adds a caveat to the README about #2535 and removes some unnecessary hard coded paths which makes development easier on platforms such as Nix

docs/scripts/classes.py

@@ -7,7 +7,7 @@
 #
 # Original Author: Jean-Roch COULON - Thales
 
-#!/usr/bin/python3
+#!/usr/bin/env python3
 
 
 class Parameter:

docs/scripts/define_blacklist.py

@@ -7,7 +7,7 @@
 #
 # Original Author: Jean-Roch COULON - Thales
 
-#!/usr/bin/python3
+#!/usr/bin/env python3
 
 
 def define_blacklist(parameters):

docs/scripts/parameters_extractor.py

@@ -7,7 +7,7 @@
 #
 # Original Author: Jean-Roch COULON - Thales
 
-#!/usr/bin/python3
+#!/usr/bin/env python3
 
 import sys
 import os

docs/scripts/spec_builder.py

@@ -7,7 +7,7 @@
 #
 # Original Author: Jean-Roch COULON - Thales
 
-#!/usr/bin/python3
+#!/usr/bin/env python3
 
 import re
 import sys

tutorials/fpga.md

@@ -35,7 +35,7 @@ We currently provide support for the [Genesys 2 board](https://reference.digilen
 
 - **Genesys 2**
 
-   - Open Vivado
+   - Open Vivado 2018.2
    - Open the hardware manager and open the target board (Genesys II - `xc7k325t`)
    - Tools - Add Configuration Memory Device
    - Select the following Spansion SPI flash `s25fl256xxxxxx0`
@@ -111,7 +111,7 @@ make clean-altera
 - **Genesys 2**
 You can debug (and program) the FPGA using [OpenOCD](http://openocd.org/doc/html/Architecture-and-Core-Commands.html). We provide two example scripts for OpenOCD below.
 
-To get started, connect the micro USB port that is labeled with JTAG to your machine. This port is attached to the FTDI 2232 USB-to-serial chip on the Genesys 2 board, and is usually used to access the native JTAG interface of the Kintex-7 FPGA (e.g. to program the device using Vivado). However, the FTDI chip also exposes a second serial link that is routed to GPIO pins on the FPGA, and we leverage this to wire up the JTAG from the RISC-V debug module.
+To get started, connect the micro USB port that is labeled with JTAG to your machine. This port is attached to the FTDI 2232 USB-to-serial chip on the Genesys 2 board, and is usually used to access the native JTAG interface of the Kintex-7 FPGA (e.g. to program the device using Vivado 2018.2). However, the FTDI chip also exposes a second serial link that is routed to GPIO pins on the FPGA, and we leverage this to wire up the JTAG from the RISC-V debug module.
 
 >If you are on an Ubuntu based system you need to add the following udev rule to `/etc/udev/rules.d/99-ftdi.rules`
 >```

vendor/pulp-platform/fpga-support/README.md

@@ -15,7 +15,7 @@ behavioral and post-synthesis simulations, set the `CF_MATH_PKG_PATH` environmen
 path where you have that package installed.
 
 Add all files in the `rtl/` folder to the list of compilation files of your development tool (e.g.,
-Xilinx Vivado).  Read the documentation (header of the source file) of the block that you want to
+Xilinx Vivado 2018.2).  Read the documentation (header of the source file) of the block that you want to
 use and use the block as described there.
 
 ## Contributing

verif/sim/cva6.py

@@ -1004,7 +1004,7 @@ def check_spike_version():
     logging.info(f"- stderr:\n\n{user_spike_stderr_string}")
     # Run 'ldd' on Spike binary and print contents of stdout and stderr.
     spike_ldd = subprocess.run(
-        "/bin/ldd $SPIKE_PATH/spike", capture_output=True, text=True, shell=True
+        "ldd $SPIKE_PATH/spike", capture_output=True, text=True, shell=True
     )
     spike_ldd_stdout = spike_ldd.stdout.strip()
     spike_ldd_stderr = spike_ldd.stderr.strip()