update Design Doc after bumping H extension (#1968)

core/include/cv32a65x_config_pkg.sv

@@ -22,7 +22,7 @@ package cva6_config_pkg;
   localparam CVA6ConfigZcbExtEn = 1;
   localparam CVA6ConfigZcmpExtEn = 0;
   localparam CVA6ConfigAExtEn = 0;
-  localparam CVA6ConfigHExtEn = 0;  // always disabled
+  localparam CVA6ConfigHExtEn = 0;
   localparam CVA6ConfigBExtEn = 1;
   localparam CVA6ConfigVExtEn = 0;
   localparam CVA6ConfigZiCondExtEn = 0;

docs/04_cv32a65x_design/source/parameters_cv32a65x.rst

@@ -84,6 +84,10 @@
      - Compress RISC-V extension
      - 1
 
+   * - RVH
+     - Hypervisor RISC-V extension
+     - 0
+
    * - RVZCB
      - Zcb RISC-V extension
      - 1
@@ -121,7 +125,7 @@
      - 64'h800
 
    * - ExceptionAddress
-     - Address to jump when exception 
+     - Address to jump when exception
      - 64'h808
 
    * - RASDepth

docs/04_cv32a65x_design/source/port_branch_unit.rst

@@ -98,6 +98,8 @@
 
 Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
 
+| As RVH = 0,
+|   ``v_i`` input is tied to 0
 | As DebugEn = 0,
 |   ``debug_mode_i`` input is tied to 0
 

docs/04_cv32a65x_design/source/port_commit_stage.rst

@@ -171,4 +171,7 @@ Due to cv32a65x configuration, some ports are tied to a static value. These port
 |   ``fence_o`` output is tied to 0
 | As RVS = 0,
 |   ``sfence_vma_o`` output is tied to 0
+| As RVH = 0,
+|   ``hfence_vvma_o`` output is tied to 0
+|   ``hfence_gvma_o`` output is tied to 0
 

docs/04_cv32a65x_design/source/port_controller.rst

@@ -128,6 +128,12 @@
 
 Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
 
+| As RVH = 0,
+|   ``v_i`` input is tied to 0
+|   ``flush_tlb_vvma_o`` output is tied to 0
+|   ``flush_tlb_gvma_o`` output is tied to 0
+|   ``hfence_vvma_i`` input is tied to 0
+|   ``hfence_gvma_i`` input is tied to 0
 | As MMUPresent = 0,
 |   ``flush_tlb_o`` output is tied to 0
 | As EnableAccelerator = 0,

docs/04_cv32a65x_design/source/port_csr_regfile.rst

@@ -190,6 +190,21 @@ Due to cv32a65x configuration, some ports are tied to a static value. These port
 |   ``tvm_o`` output is tied to 0
 |   ``tw_o`` output is tied to 0
 |   ``tsr_o`` output is tied to 0
+| As RVH = 0,
+|   ``v_o`` output is tied to 0
+|   ``vfs_o`` output is tied to 0
+|   ``en_g_translation_o`` output is tied to 0
+|   ``en_ld_st_g_translation_o`` output is tied to 0
+|   ``ld_st_v_o`` output is tied to 0
+|   ``csr_hs_ld_st_inst_i`` input is tied to 0
+|   ``vs_sum_o`` output is tied to 0
+|   ``vmxr_o`` output is tied to 0
+|   ``vsatp_ppn_o`` output is tied to 0
+|   ``vs_asid_o`` output is tied to 0
+|   ``hgatp_ppn_o`` output is tied to 0
+|   ``vmid_o`` output is tied to 0
+|   ``vtw_o`` output is tied to 0
+|   ``hu_o`` output is tied to 0
 | As RVV = 0,
 |   ``vs_o`` output is tied to 0
 | As RVS = 0,

docs/04_cv32a65x_design/source/port_decoder.rst

@@ -118,6 +118,11 @@ Due to cv32a65x configuration, some ports are tied to a static value. These port
 |   ``tvm_i`` input is tied to 0
 |   ``tw_i`` input is tied to 0
 |   ``tsr_i`` input is tied to 0
+| As RVH = 0,
+|   ``v_i`` input is tied to 0
+|   ``vfs_i`` input is tied to 0
+|   ``vtw_i`` input is tied to 0
+|   ``hu_i`` input is tied to 0
 | As RVF = 0,
 |   ``fs_i`` input is tied to 0
 |   ``frm_i`` input is tied to 0

docs/04_cv32a65x_design/source/port_ex_stage.rst

@@ -346,6 +346,21 @@ Due to cv32a65x configuration, some ports are tied to a static value. These port
 
 | As DebugEn = 0,
 |   ``debug_mode_i`` input is tied to 0
+| As RVH = 0,
+|   ``tinst_i`` input is tied to 0
+|   ``enable_g_translation_i`` input is tied to 0
+|   ``en_ld_st_g_translation_i`` input is tied to 0
+|   ``flush_tlb_vvma_i`` input is tied to 0
+|   ``flush_tlb_gvma_i`` input is tied to 0
+|   ``v_i`` input is tied to 0
+|   ``ld_st_v_i`` input is tied to 0
+|   ``csr_hs_ld_st_inst_o`` output is tied to 0
+|   ``vs_sum_i`` input is tied to 0
+|   ``vmxr_i`` input is tied to 0
+|   ``vsatp_ppn_i`` input is tied to 0
+|   ``vs_asid_i`` input is tied to 0
+|   ``hgatp_ppn_i`` input is tied to 0
+|   ``vmid_i`` input is tied to 0
 | As EnableAccelerator = 0,
 |   ``stall_st_pending_i`` input is tied to 0
 |   ``acc_valid_i`` input is tied to 0

docs/04_cv32a65x_design/source/port_id_stage.rst

@@ -108,6 +108,11 @@ Due to cv32a65x configuration, some ports are tied to a static value. These port
 |   ``tvm_i`` input is tied to 0
 |   ``tw_i`` input is tied to 0
 |   ``tsr_i`` input is tied to 0
+| As RVH = 0,
+|   ``v_i`` input is tied to 0
+|   ``vfs_i`` input is tied to 0
+|   ``vtw_i`` input is tied to 0
+|   ``hu_i`` input is tied to 0
 | As RVF = 0,
 |   ``fs_i`` input is tied to 0
 |   ``frm_i`` input is tied to 0

docs/04_cv32a65x_design/source/port_instr_queue.rst

@@ -120,4 +120,10 @@
      - ID_STAGE
      - logic
 
+Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
+
+| As RVH = 0,
+|   ``exception_gpaddr_i`` input is tied to 0
+|   ``exception_tinst_i`` input is tied to 0
+|   ``exception_gva_i`` input is tied to 0
 

docs/04_cv32a65x_design/source/port_issue_read_operands.rst

@@ -250,6 +250,8 @@ Due to cv32a65x configuration, some ports are tied to a static value. These port
 
 | As EnableAccelerator = 0,
 |   ``stall_i`` input is tied to 0
+| As RVH = 0,
+|   ``tinst_o`` output is tied to 0
 | As RVF = 0,
 |   ``fpu_ready_i`` input is tied to 0
 |   ``fpu_valid_o`` output is tied to 0

docs/04_cv32a65x_design/source/port_issue_stage.rst

@@ -249,6 +249,8 @@ Due to cv32a65x configuration, some ports are tied to a static value. These port
 |   ``stall_i`` input is tied to 0
 |   ``issue_instr_o`` output is tied to 0
 |   ``issue_instr_hs_o`` output is tied to 0
+| As RVH = 0,
+|   ``tinst_o`` output is tied to 0
 | As RVF = 0,
 |   ``fpu_ready_i`` input is tied to 0
 |   ``fpu_valid_o`` output is tied to 0

docs/04_cv32a65x_design/source/port_load_store_unit.rst

@@ -186,6 +186,23 @@ Due to cv32a65x configuration, some ports are tied to a static value. These port
 |   ``amo_valid_commit_i`` input is tied to 0
 |   ``amo_req_o`` output is tied to 0
 |   ``amo_resp_i`` input is tied to 0
+| As RVH = 0,
+|   ``tinst_i`` input is tied to 0
+|   ``enable_g_translation_i`` input is tied to 0
+|   ``en_ld_st_g_translation_i`` input is tied to 0
+|   ``v_i`` input is tied to 0
+|   ``ld_st_v_i`` input is tied to 0
+|   ``csr_hs_ld_st_inst_o`` output is tied to 0
+|   ``vs_sum_i`` input is tied to 0
+|   ``vmxr_i`` input is tied to 0
+|   ``vsatp_ppn_i`` input is tied to 0
+|   ``vs_asid_i`` input is tied to 0
+|   ``hgatp_ppn_i`` input is tied to 0
+|   ``vmid_i`` input is tied to 0
+|   ``vmid_to_be_flushed_i`` input is tied to 0
+|   ``gpaddr_to_be_flushed_i`` input is tied to 0
+|   ``flush_tlb_vvma_i`` input is tied to 0
+|   ``flush_tlb_gvma_i`` input is tied to 0
 | As RVS = 0,
 |   ``enable_translation_i`` input is tied to 0
 |   ``en_ld_st_translation_i`` input is tied to 0

docs/04_cv32a65x_design/source/port_load_unit.rst

@@ -146,6 +146,10 @@
 
 Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
 
+| As RVH = 0,
+|   ``tinst_o`` output is tied to 0
+|   ``hs_ld_st_inst_o`` output is tied to 0
+|   ``hlvx_inst_o`` output is tied to 0
 | For any HW configuration,
 |   ``dtlb_hit_i`` input is tied to 1
 | As MMUPresent = 0,

docs/04_cv32a65x_design/source/port_store_unit.rst

@@ -164,6 +164,10 @@ Due to cv32a65x configuration, some ports are tied to a static value. These port
 |   ``amo_resp_i`` input is tied to 0
 | As IsRVFI = 0,
 |   ``rvfi_mem_paddr_o`` output is tied to 0
+| As RVH = 0,
+|   ``tinst_o`` output is tied to 0
+|   ``hs_ld_st_inst_o`` output is tied to 0
+|   ``hlvx_inst_o`` output is tied to 0
 | For any HW configuration,
 |   ``dtlb_hit_i`` input is tied to 1
 

docs/scripts/define_blacklist.py

@@ -45,6 +45,57 @@ def define_blacklist(parameters):
         black_list["single_step_o"] = [f"As {param} = {paramvalue}", "0"]
         black_list["single_step_i"] = [f"As {param} = {paramvalue}", "0"]
 
+    param = "RVH"
+    paramvalue = parameters[param].value
+    if paramvalue == "0":
+        black_list["v_i"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["v_o"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["vfs_o"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["vfs_i"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["hfence_vvma_o"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["hfence_gvma_o"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["flush_tlb_vvma_i"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["flush_tlb_gvma_i"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["flush_tlb_vvma_o"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["flush_tlb_gvma_o"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["en_g_translation_o"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["enable_g_translation_i"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["en_ld_st_g_translation_o"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["en_ld_st_g_translation_i"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["ld_st_v_o"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["ld_st_v_i"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["csr_hs_ld_st_inst_i"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["csr_hs_ld_st_inst_o"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["vs_sum_i"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["vs_sum_o"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["vmxr_o"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["vmxr_i"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["vsatp_ppn_o"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["vsatp_ppn_i"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["vs_asid_o"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["vs_asid_i"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["hgatp_ppn_o"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["hgatp_ppn_i"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["vmid_o"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["vmid_i"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["vtw_o"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["vtw_i"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["hu_o"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["hu_i"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["ld_st_v_i"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["tinst_i"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["tinst_o"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["csr_hs_ld_st_inst_o"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["exception_gpaddr_i"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["exception_tinst_i"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["exception_gva_i"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["hs_ld_st_inst_o"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["hlvx_inst_o"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["hfence_vvma_i"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["hfence_gvma_i"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["vmid_to_be_flushed_i"] = [f"As {param} = {paramvalue}", "0"]
+        black_list["gpaddr_to_be_flushed_i"] = [f"As {param} = {paramvalue}", "0"]
+
     param = "RVV"
     paramvalue = parameters[param].value
     if paramvalue == "0":