github-mirrors/cva6
1
0
Fork 0
mirror of https://github.com/openhwgroup/cva6.git synced 2025-06-27 17:00:57 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

Dev/hpdcache fpga (#2586)

Browse source 
Set HPDCACHE as default cache for FPGA boot configuration ie. cv32a6_imac_sv32
This commit is contained in:
Guillaume Chauvon 2024-11-07 16:50:48 +01:00 • committed by GitHub
parent aea4e3d174
commit 65285e5498
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
4 changed files with 170 additions and 7 deletions
Download patch file Download diff file Expand all files Collapse all files

5
Makefile
View file

@ -235,7 +235,7 @@ uart_src_sv:= corev_apu/fpga/src/apb_uart/src/slib_clock_div.sv \
corev_apu/fpga/src/apb_uart/src/apb_uart_wrap.sv
uart_src_sv := $(addprefix $(root-dir), $(uart_src_sv))
fpga_src := $(wildcard corev_apu/fpga/src/*.sv) $(wildcard corev_apu/fpga/src/ariane-ethernet/*.sv) common/local/util/tc_sram_fpga_wrapper.sv vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx64.sv
fpga_src := $(wildcard corev_apu/fpga/src/*.sv) $(wildcard corev_apu/fpga/src/ariane-ethernet/*.sv) common/local/util/tc_sram_fpga_wrapper.sv common/local/util/hpdcache_sram_1rw.sv common/local/util/hpdcache_sram_wbyteenable_1rw.sv vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx64.sv vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx32.sv vendor/pulp-platform/fpga-support/rtl/SyncSpRam.sv
fpga_src := $(addprefix $(root-dir), $(fpga_src)) src/bootrom/bootrom_$(XLEN).sv
# look for testbenches
@ -733,6 +733,9 @@ fpga_filter += $(addprefix $(root-dir), vendor/pulp-platform/tech_cells_generic/
fpga_filter += $(addprefix $(root-dir), common/local/util/tc_sram_wrapper.sv)
fpga_filter += $(addprefix $(root-dir), corev_apu/tb/ariane_peripherals.sv)
fpga_filter += $(addprefix $(root-dir), corev_apu/tb/ariane_testharness.sv)
fpga_filter += $(addprefix $(root-dir), core/cache_subsystem/hpdcache/rtl/src/common/macros/behav/hpdcache_sram_1rw.sv)
fpga_filter += $(addprefix $(root-dir), core/cache_subsystem/hpdcache/rtl/src/common/macros/behav/hpdcache_sram_wbyteenable_1rw.sv)
fpga_filter += $(addprefix $(root-dir), core/cache_subsystem/hpdcache/rtl/src/common/macros/behav/hpdcache_sram_wmask_1rw.sv)
src/bootrom/bootrom_$(XLEN).sv:
$(MAKE) -C corev_apu/fpga/src/bootrom BOARD=$(BOARD) XLEN=$(XLEN) bootrom_$(XLEN).sv

46
common/local/util/hpdcache_sram_1rw.sv Normal file
View file

@ -0,0 +1,46 @@
// Copyright 2025 Thales DIS France SAS
//
// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
// You may obtain a copy of the License at https://solderpad.org/licenses/
//
// Original Author: Yannick Casamatta - Thales
// Date: 22/10/2024
module hpdcache_sram_1rw
#(
parameter int unsigned ADDR_SIZE = 0,
parameter int unsigned DATA_SIZE = 0,
parameter int unsigned DEPTH = 2**ADDR_SIZE
)
(
input logic clk,
input logic rst_n,
input logic cs,
input logic we,
input logic [ADDR_SIZE-1:0] addr,
input logic [DATA_SIZE-1:0] wdata,
output logic [DATA_SIZE-1:0] rdata
);
SyncSpRam #(
.ADDR_WIDTH(ADDR_SIZE),
.DATA_DEPTH(DEPTH), // usually 2**ADDR_WIDTH, but can be lower
.DATA_WIDTH(DATA_SIZE),
.OUT_REGS (0),
.SIM_INIT (1) // for simulation only, will not be synthesized
// 0: no init, 1: zero init, 2: random init
// note: on verilator, 2 is not supported. define the VERILATOR macro to work around.
)SyncSpRam_i(
.Clk_CI (clk),
.Rst_RBI (rst_n),
.CSel_SI (cs),
.WrEn_SI (we),
.Addr_DI (addr),
.WrData_DI(wdata),
.RdData_DO(rdata)
);
endmodule : hpdcache_sram_1rw

114
common/local/util/hpdcache_sram_wbyteenable_1rw.sv Normal file
View file

@ -0,0 +1,114 @@
// Copyright 2025 Thales DIS France SAS
//
// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
// You may obtain a copy of the License at https://solderpad.org/licenses/
//
// Original Author: Yannick Casamatta - Thales
// Date: 22/10/2024
module hpdcache_sram_wbyteenable_1rw
#(
parameter int unsigned ADDR_SIZE = 0,
parameter int unsigned DATA_SIZE = 0,
parameter int unsigned DEPTH = 2**ADDR_SIZE
)
(
input logic clk,
input logic rst_n,
input logic cs,
input logic we,
input logic [ADDR_SIZE-1:0] addr,
input logic [DATA_SIZE-1:0] wdata,
input logic [DATA_SIZE/8-1:0] wbyteenable,
output logic [DATA_SIZE-1:0] rdata
);
if (DATA_SIZE == 128) begin
// Découpage des données en deux moitiés de 64 bits
logic [DATA_SIZE/2-1:0] wdata_low, wdata_high;
logic [DATA_SIZE/2-1:0] rdata_low, rdata_high;
logic [7:0] be_low, be_high;
assign wdata_low = wdata[63:0];
assign wdata_high = wdata[127:64];
assign be_low = wbyteenable[7:0];
assign be_high = wbyteenable[15:8];
SyncSpRamBeNx64 #(
.ADDR_WIDTH(ADDR_SIZE),
.DATA_DEPTH(DEPTH),
.OUT_REGS (0),
.SIM_INIT (1)
) SyncSpRam_0 (
.Clk_CI (clk),
.Rst_RBI (rst_n),
.CSel_SI (cs),
.WrEn_SI (we), // Ecriture sur la banque basse
.BEn_SI (be_low),
.Addr_DI (addr),
.WrData_DI(wdata_low),
.RdData_DO(rdata_low)
);
SyncSpRamBeNx64 #(
.ADDR_WIDTH(ADDR_SIZE),
.DATA_DEPTH(DEPTH),
.OUT_REGS (0),
.SIM_INIT (1)
) SyncSpRam_1 (
.Clk_CI (clk),
.Rst_RBI (rst_n),
.CSel_SI (cs),
.WrEn_SI (we), // Ecriture sur la banque haute
.BEn_SI (be_high),
.Addr_DI (addr),
.WrData_DI(wdata_high),
.RdData_DO(rdata_high)
);
assign rdata = {rdata_high, rdata_low};
end else if (DATA_SIZE == 64) begin
SyncSpRamBeNx64 #(
.ADDR_WIDTH(ADDR_SIZE),
.DATA_DEPTH(DEPTH), // usually 2**ADDR_WIDTH, but can be lower
.OUT_REGS (0),
.SIM_INIT (1) // for simulation only, will not be synthesized
// 0: no init, 1: zero init, 2: random init
// note: on verilator, 2 is not supported. define the VERILATOR macro to work around.
)SyncSpRam_i(
.Clk_CI (clk),
.Rst_RBI (rst_n),
.CSel_SI (cs),
.WrEn_SI (we),
.BEn_SI (wbyteenable),
.Addr_DI (addr),
.WrData_DI(wdata),
.RdData_DO(rdata)
);
end else if (DATA_SIZE == 32) begin
SyncSpRamBeNx32 #(
.ADDR_WIDTH(ADDR_SIZE),
.DATA_DEPTH(DEPTH), // usually 2**ADDR_WIDTH, but can be lower
.OUT_REGS (0),
.SIM_INIT (1) // for simulation only, will not be synthesized
// 0: no init, 1: zero init, 2: random init
// note: on verilator, 2 is not supported. define the VERILATOR macro to work around.
)SyncSpRam_i(
.Clk_CI (clk),
.Rst_RBI (rst_n),
.CSel_SI (cs),
.WrEn_SI (we),
.BEn_SI (wbyteenable),
.Addr_DI (addr),
.WrData_DI(wdata),
.RdData_DO(rdata)
);
end else begin
$fatal(1, "DATASIZE=%d, in not supported " ,DATA_SIZE);
end
endmodule : hpdcache_sram_wbyteenable_1rw

12
core/include/cv32a6_imac_sv32_config_pkg.sv
View file

@ -43,8 +43,8 @@ package cva6_config_pkg;
localparam CVA6ConfigDcacheSetAssoc = 8;
localparam CVA6ConfigDcacheLineWidth = 128;
localparam CVA6ConfigDcacheIdWidth = 1;
localparam CVA6ConfigMemTidWidth = 2;
localparam CVA6ConfigDcacheIdWidth = 3;
localparam CVA6ConfigMemTidWidth = 4;
localparam CVA6ConfigWtDcacheWbufDepth = 8;
@ -66,7 +66,7 @@ package cva6_config_pkg;
localparam CVA6ConfigPerfCounterEn = 1;
localparam config_pkg::cache_type_t CVA6ConfigDcacheType = config_pkg::WT;
localparam config_pkg::cache_type_t CVA6ConfigDcacheType = config_pkg::HPDCACHE;
localparam CVA6ConfigMmuPresent = 1;
@ -120,9 +120,9 @@ package cva6_config_pkg;
PMPAddrRstVal: {64{64'h0}},
PMPEntryReadOnly: 64'd0,
NOCType: config_pkg::NOC_TYPE_AXI4_ATOP,
NrNonIdempotentRules: unsigned'(2),
NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
NonIdempotentLength: 1024'({64'b0, 64'b0}),
NrNonIdempotentRules: unsigned'(1),
NonIdempotentAddrBase: 1024'({64'b0}),
NonIdempotentLength: 1024'({64'h8000_0000}),
NrExecuteRegionRules: unsigned'(3),
ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),