update riscv-isa-manual to riscv-isa-release-2c07aa2-2024-10-18 (#2560)

Since last riscv-isa-manual update (CVA6 commit 3059b1cb2):
        - Privileged Architecture 1.13 ratified
        - minor documentation changes
        - wavedrom file renamed to .edn

docs/04_cv32a65x/config/config.adoc

@@ -28,6 +28,7 @@
 :RVZihpm: false
 :RVZimop: false
 :RVZk: false
+:RVZpm: false
 :RVZsmcdeleg: false
 :RVZsmcntrpmf: false
 :RVZsmcsrind-RVZsscsrind: false

docs/04_cv32a65x/riscv/priv-isa-cv32a65x.html

@@ -440,7 +440,8 @@ body.book #toc,body.book #preamble,body.book h1.sect0,body.book .sect1>h2{page-b
 <div id="header">
 <h1>The RISC-V Instruction Set Manual for CV32A65X: Volume II: Privileged Architecture</h1>
 <div class="details">
-<span id="revnumber">version 20240801</span>
+<span id="revnumber">version 20241017</span>
+<br><span id="revremark">This document is in Ratified state.</span>
 </div>
 <div id="toc" class="toc2">
 <div id="toctitle">Table of Contents</div>
@@ -564,10 +565,11 @@ body.book #toc,body.book #preamble,body.book h1.sect0,body.book .sect1>h2{page-b
 <li><a href="#hypervisor">14. "H" Extension for Hypervisor Support, Version 1.0</a></li>
 <li><a href="#priv-cfi">15. Control-flow Integrity (CFI)</a></li>
 <li><a href="#ssdbltrp">16. "Ssdbltrp" Double Trap Extension, Version 1.0</a></li>
-<li><a href="#_risc_v_privileged_instruction_set_listings">17. RISC-V Privileged Instruction Set Listings</a></li>
+<li><a href="#Zpm">17. Pointer Masking Extensions, Version 1.0.0</a></li>
-<li><a href="#_history">18. History</a>
+<li><a href="#_risc_v_privileged_instruction_set_listings">18. RISC-V Privileged Instruction Set Listings</a></li>
+<li><a href="#_history">19. History</a>
 <ul class="sectlevel2">
-<li><a href="#_research_funding_at_uc_berkeley">18.1. Research Funding at UC Berkeley</a></li>
+<li><a href="#_research_funding_at_uc_berkeley">19.1. Research Funding at UC Berkeley</a></li>
 </ul>
 </li>
 <li><a href="#_bibliography">Bibliography</a></li>
@@ -590,11 +592,11 @@ Avižienis, Jacob Bachmeyer, Allen J. Baum, Jonathan Behrens, Paolo Bonzini, Rus
 Christopher Celio, Chuanhua Chang, David Chisnall, Anthony Coulter, Palmer Dabbelt, Monte
 Dalrymple, Paul Donahue, Greg Favor, Dennis Ferguson,  Marc Gauthier, Andy Glew,
 Gary Guo, Mike Frysinger, John Hauser, David Horner, Olof
-Johansson, David Kruckemyer, Yunsup Lee, Daniel Lustig, Andrew Lutomirski, Prashanth Mundkur,
+Johansson, David Kruckemyer, Yunsup Lee, Daniel Lustig, Andrew Lutomirski, Martin Maas, Prashanth Mundkur,
 Jonathan Neuschäfer, Rishiyur
 Nikhil, Stefan O&#8217;Rear, Albert Ou, John Ousterhout, David Patterson, Dmitri
 Pavlov, Kade Phillips, Josh Scheid, Colin Schmidt, Michael Taylor, Wesley Terpstra, Matt Thomas, Tommy Thorn, Ray
-VanDeWalker, Megan Wachs, Steve Wallach, Andrew Waterman, Claire Wolf,
+VanDeWalker, Megan Wachs, Steve Wallach, Andrew Waterman, Claire Wolf, Adam Zabrocki,
 and Reinoud Zandijk..</em></p>
 </div>
 <div class="paragraph">
@@ -623,11 +625,11 @@ Jean-Roch Coulon, André Sintzoff.</em></p>
 OpenHW Group CV32A65X.</p>
 </div>
 <div class="paragraph">
-<p><strong class="big"><em>Preface to Version 20240801</em></strong></p>
+<p><strong class="big"><em>Preface to Version 20241017</em></strong></p>
 </div>
 <div class="paragraph">
 <p>This document describes the RISC-V privileged architecture. This
-release, version 20240801, contains the following versions of the RISC-V ISA
+release, version 20241017, contains the following versions of the RISC-V ISA
 modules:</p>
 </div>
 <table class="tableblock frame-all grid-all fit-content center">
@@ -645,15 +647,15 @@ modules:</p>
 </thead>
 <tbody>
 <tr>
-<td class="tableblock halign-center valign-top"><p class="tableblock"><em>Machine ISA</em><br>
+<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Machine ISA</strong><br>
 <strong>Smstateen Extension</strong><br>
 <strong>Smcsrind/Sscsrind Extension</strong><br>
 <strong>Smepmp</strong><br>
 <strong>Smcntrpmf</strong><br>
 <strong>Smrnmi Extension</strong><br>
 <strong>Smcdeleg</strong><br>
-<em>Smdbltrp</em><br>
+<strong>Smdbltrp</strong><br>
-<em>Supervisor ISA</em><br>
+<strong>Supervisor ISA</strong><br>
 <strong>Svade Extension</strong><br>
 <strong>Svnapot Extension</strong><br>
 <strong>Svpbmt Extension</strong><br>
@@ -661,19 +663,21 @@ modules:</p>
 <strong>Svadu Extension</strong><br>
 <strong>Sstc</strong><br>
 <strong>Sscofpmf</strong><br>
-<em>Ssdbltrp</em><br>
+<strong>Ssdbltrp</strong><br>
 <strong>Hypervisor ISA</strong><br>
-<em>Shlcofideleg</em><br>
+<strong>Shlcofideleg</strong><br>
 <strong>Svvptc</strong></p></td>
-<td class="tableblock halign-left valign-top"><p class="tableblock"><em>1.13</em><br>
+<td class="tableblock halign-left valign-top"><p class="tableblock"><strong>1.13</strong><br>
-<strong>1.0</strong><br>
+<strong>1.0</strong><br>
-<strong>1.0</strong><br>
+<strong>1.0</strong><br>
-<strong>1.0</strong><br>
+<strong>1.0</strong><br>
-<strong>1.0</strong><br>
+<strong>1.0</strong><br>
-<strong>1.0</strong><br>
+<strong>1.0</strong><br>
-<strong>1.0</strong><br>
+<strong>1.0</strong><br>
-<em>1.0</em><br>
+<strong>1.0</strong><br>
-<em>1.13</em><br>
+<strong>1.13</strong><br>
+<strong>1.0</strong><br>
+<strong>1.0</strong><br>
 <strong>1.0</strong><br>
 <strong>1.0</strong><br>
 <strong>1.0</strong><br>
@@ -681,19 +685,19 @@ modules:</p>
 <strong>1.0</strong><br>
 <strong>1.0</strong><br>
 <strong>1.0</strong><br>
-<em>1.0</em><br>
 <strong>1.0</strong><br>
-<em>0.1</em><br>
 <strong>1.0</strong></p></td>
-<td class="tableblock halign-center valign-top"><p class="tableblock"><em>Draft</em><br>
+<td class="tableblock halign-center valign-top"><p class="tableblock"><strong>Ratified</strong><br>
-<strong>Ratified</strong><br>
+<strong>Ratified</strong><br>
-<strong>Ratified</strong><br>
+<strong>Ratified</strong><br>
-<strong>Ratified</strong><br>
+<strong>Ratified</strong><br>
-<strong>Ratified</strong><br>
+<strong>Ratified</strong><br>
-<strong>Ratified</strong><br>
+<strong>Ratified</strong><br>
-<strong>Ratified</strong><br>
+<strong>Ratified</strong><br>
-<em>Draft</em><br>
+<strong>Ratified</strong><br>
-<em>Draft</em><br>
+<strong>Ratified</strong><br>
+<strong>Ratified</strong><br>
+<strong>Ratified</strong><br>
 <strong>Ratified</strong><br>
 <strong>Ratified</strong><br>
 <strong>Ratified</strong><br>
@@ -701,9 +705,7 @@ modules:</p>
 <strong>Ratified</strong><br>
 <strong>Ratified</strong><br>
 <strong>Ratified</strong><br>
-<em>Draft</em><br>
 <strong>Ratified</strong><br>
-<em>Draft</em><br>
 <strong>Ratified</strong></p></td>
 </tr>
 </tbody>
@@ -2184,10 +2186,10 @@ SRO</p></td>
 <code>stval</code><br>
 <code>sip</code><br>
 <code>scountovf</code></p></td>
-<td class="tableblock halign-left valign-top"><p class="tableblock">Scratch register for supervisor trap handlers.<br>
+<td class="tableblock halign-left valign-top"><p class="tableblock">Supervisor scratch register.<br>
 Supervisor exception program counter.<br>
 Supervisor trap cause.<br>
-Supervisor bad address or instruction.<br>
+Supervisor trap value.<br>
 Supervisor interrupt pending.<br>
 Supervisor count overflow.</p></td>
 </tr>
@@ -2302,7 +2304,7 @@ HRO</p></td>
 <code>hvip</code><br>
 <code>htinst</code><br>
 <code>hgeip</code></p></td>
-<td class="tableblock halign-left valign-top"><p class="tableblock">Hypervisor bad guest physical address.<br>
+<td class="tableblock halign-left valign-top"><p class="tableblock">Hypervisor trap value.<br>
 Hypervisor interrupt pending.<br>
 Hypervisor virtual interrupt pending.<br>
 Hypervisor trap instruction (transformed).<br>
@@ -2426,7 +2428,7 @@ Virtual supervisor trap handler base address.<br>
 Virtual supervisor scratch register.<br>
 Virtual supervisor exception program counter.<br>
 Virtual supervisor trap cause.<br>
-Virtual supervisor bad address or instruction.<br>
+Virtual supervisor trap value.<br>
 Virtual supervisor interrupt pending.<br>
 Virtual supervisor address translation and protection.</p></td>
 </tr>
@@ -2541,13 +2543,13 @@ MRW</p></td>
 <code>mip</code><br>
 <code>mtinst</code><br>
 <code>mtval2</code></p></td>
-<td class="tableblock halign-left valign-top"><p class="tableblock">Scratch register for machine trap handlers.<br>
+<td class="tableblock halign-left valign-top"><p class="tableblock">Machine scratch register.<br>
 Machine exception program counter.<br>
 Machine trap cause.<br>
-Machine bad address or instruction.<br>
+Machine trap value.<br>
 Machine interrupt pending.<br>
 Machine trap instruction (transformed).<br>
-Machine bad guest physical address.</p></td>
+Machine second trap value.</p></td>
 </tr>
 <tr>
 <td class="tableblock halign-center valign-top" colspan="4"><p class="tableblock">Machine Configuration</p></td>
@@ -3858,6 +3860,9 @@ Counter-overflow interrupt<br>
 0<br>
 0<br>
 0<br>
+0<br>
+0<br>
+0<br>
 0</p></td>
 <td class="tableblock halign-right valign-top"><p class="tableblock">0<br>
 1<br>
@@ -4448,10 +4453,8 @@ access-fault exception.</p>
 <div class="paragraph">
 <p>The A field in a PMP entry&#8217;s configuration register encodes the
 address-matching mode of the associated PMP address register. The
-encoding of this field is shown in <a href="#pmpcfg-a">Table 14</a>.</p>
+encoding of this field is shown in <a href="#pmpcfg-a">Table 14</a>.
-</div>
+When A=0, this PMP entry is disabled and matches no addresses. Two other
-<div class="paragraph">
-<p>When A=0, this PMP entry is disabled and matches no addresses. Two other
 address-matching modes are supported: naturally aligned power-of-2
 regions (NAPOT), including the special case of naturally aligned
 four-byte regions (NA4); and the top boundary of an arbitrary range
@@ -4679,7 +4682,15 @@ check the PMP settings synchronously.</p>
 </div>
 </div>
 <div class="sect1">
-<h2 id="_risc_v_privileged_instruction_set_listings">17. RISC-V Privileged Instruction Set Listings</h2>
+<h2 id="Zpm">17. Pointer Masking Extensions, Version 1.0.0</h2>
+<div class="sectionbody">
+<div class="paragraph">
+<p>CV32A65X: These extensions are not supported.</p>
+</div>
+</div>
+</div>
+<div class="sect1">
+<h2 id="_risc_v_privileged_instruction_set_listings">18. RISC-V Privileged Instruction Set Listings</h2>
 <div class="sectionbody">
 <div class="paragraph">
 <p>This chapter presents instruction-set listings for all instructions
@@ -4699,10 +4710,10 @@ manual.</p>
 </div>
 </div>
 <div class="sect1">
-<h2 id="_history">18. History</h2>
+<h2 id="_history">19. History</h2>
 <div class="sectionbody">
 <div class="sect2">
-<h3 id="_research_funding_at_uc_berkeley">18.1. Research Funding at UC Berkeley</h3>
+<h3 id="_research_funding_at_uc_berkeley">19.1. Research Funding at UC Berkeley</h3>
 <div class="paragraph">
 <p>Development of the RISC-V architecture and implementations has been
 partially funded by the following sponsors.</p>
@@ -4747,7 +4758,7 @@ inferred.</p>
 </div>
 <div id="footer">
 <div id="footer-text">
-Version 20240801<br>
+Version 20241017<br>
 </div>
 </div>
 </body>

docs/06_cv64a6_mmu/config/config.adoc

@@ -8,6 +8,7 @@
 :SV: SV0
 :RVZicfilp: false
 :RVZicfiss: false
+:RVZpm: false
 :RVZsmstateen: false
 :RVZsmcsrind-RVZsscsrind: false
 :RVZsmepmp: false

docs/riscv-isa/riscv-isa-manual

@@ -1 +1 @@
-Subproject commit 5ddbdd678a03dc1d7801d4ef5bb143375cae5a43
+Subproject commit 2c07aa2bcc02fd5fb2e53e42a32dc62a3eb0aa62

docs/riscv-isa/src/colophon.adoc

@@ -7,7 +7,7 @@
 This document describes the RISC-V unprivileged architecture tailored for
 OpenHW Group {ohg-config}.
 
-[.big]*_Preface to Document Version 20240801_*
+[.big]*_Preface to Document Version 20241017_*
 
 This document describes the RISC-V unprivileged architecture.
 

docs/riscv-isa/src/counters.adoc

@@ -27,7 +27,7 @@ Some execution environments might prohibit access to counters, for
 example, to impede timing side-channel attacks.
 ====
 
-include::images/wavedrom/counters-diag.adoc[]
+include::images/wavedrom/counters-diag.edn[]
 
 
 For base ISAs with XLEN≥64, CSR instructions can access

docs/riscv-isa/src/machine.adoc

@@ -300,7 +300,7 @@ endif::[]
 //image::png/mvendorid.png[align="center"]
 
 .Vendor ID register (`mvendorid`)
-include::images/bytefield/mvendorid.adoc[]
+include::images/bytefield/mvendorid.edn[]
 
 ifdef::archi-default[]
 JEDEC manufacturer IDs are ordinarily encoded as a sequence of one-byte
@@ -348,7 +348,7 @@ of the hart supplied to CVA6, 0x3.
 endif::[]
 
 .Machine Architecture ID (`marchid`) register
-include::images/bytefield/marchid.adoc[]
+include::images/bytefield/marchid.edn[]
 
 ifdef::archi-default[]
 Open-source project architecture IDs are allocated globally by RISC-V
@@ -410,7 +410,7 @@ processor itself and not any surrounding system.
 endif::[]
 
 .Machine Implementation ID (`mimpid`) register
-include::images/bytefield/mimpid.adoc[]
+include::images/bytefield/mimpid.edn[]
 
 ifeval::[{note} == true]
 [NOTE]
@@ -443,7 +443,7 @@ Hart ID is zero.
 endif::[]
 
 .Hart ID (`mhartid`) register
-include::images/bytefield/mhartid.adoc[]
+include::images/bytefield/mhartid.edn[]
 
 ifeval::[{note} == true]
 [NOTE]
@@ -487,13 +487,13 @@ endif::[]
 ifdef::archi-default,XLEN-32[]
 [[mstatusreg-rv32]]
 .Machine-mode status (`mstatus`) register for RV32
-include::images/wavedrom/mstatusreg-rv321.adoc[]
+include::images/wavedrom/mstatusreg-rv321.edn[]
 endif::[]
 
 ifdef::archi-default,XLEN-64[]
 [[mstatusreg]]
 .Machine-mode status (`mstatus`) register for RV64
-include::images/wavedrom/mstatusreg.adoc[]
+include::images/wavedrom/mstatusreg.edn[]
 endif::[]
 
 ifdef::archi-default[]
@@ -509,7 +509,7 @@ endif::[]
 ifdef::archi-default,XLEN-32[]
 [[mstatushreg]]
 .Additional machine-mode status (`mstatush`) register  for RV32.
-include::images/wavedrom/mstatushreg.adoc[]
+include::images/wavedrom/mstatushreg.edn[]
 endif::[]
 
 [[privstack]]
@@ -1606,7 +1606,7 @@ and a vector mode (MODE).
 
 
 .Encoding of mtvec MODE field.
-include::images/bytefield/mtvec.adoc[]
+include::images/bytefield/mtvec.edn[]
 
 ifdef::archi-default[]
 The `mtvec` register must always be implemented, but can contain a
@@ -1774,7 +1774,7 @@ endif::[]
 
 ifdef::archi-default,RVS-true[]
 .Machine Exception Delegation (`medeleg`) register.
-include::images/bytefield/medeleg.adoc[]
+include::images/bytefield/medeleg.edn[]
 
 `medeleg` has a bit position allocated for every synchronous exception
 shown in <<mcauses>>, with the index of the
@@ -1794,7 +1794,7 @@ endif::[]
 
 ifdef::archi-default,RVS-true[]
 .Machine Interrupt Delegation (`mideleg`) Register.
-include::images/bytefield/mideleg.adoc[]
+include::images/bytefield/mideleg.edn[]
 
 `mideleg` holds trap delegation bits for individual interrupts, with the
 layout of bits matching those in the `mip` register (i.e., STIP
@@ -1833,10 +1833,10 @@ at the platform's discretion.
 endif::[]
 
 .Machine Interrupt-Pending (`mip`) register.
-include::images/bytefield/mideleg.adoc[]
+include::images/bytefield/mideleg.edn[]
 
 .Machine Interrupt-Enable (`mie`) register
-include::images/bytefield/mideleg.adoc[]
+include::images/bytefield/mideleg.edn[]
 
 ifdef::archi-default[]
 An interrupt _i_ will trap to M-mode (causing the privilege mode to
@@ -1883,11 +1883,11 @@ formatted as shown in <<mipreg-standard>> and <<miereg-standard>> respectively.
 
 [[mipreg-standard]]
 .Standard portion (bits 15:0) of `mip`.
-include::images/bytefield/mipreg-standard.adoc[]
+include::images/bytefield/mipreg-standard.edn[]
 
 [[miereg-standard]]
 .Standard portion (bits 15:0) of `mie`.
-include::images/bytefield/miereg-standard.adoc[]
+include::images/bytefield/miereg-standard.edn[]
 endif::[]
 
 ifeval::[{note} == true]
@@ -2055,11 +2055,12 @@ formatted as shown in <<mipreg-standard>> and <<miereg-standard>> respectively.
 
 [[mipreg-standard]]
 .Standard portion (bits 15:0) of `mip`.
-include::images/bytefield/mipreg-standard.adoc[]
+include::images/bytefield/mipreg-standard.edn[]
 
 [[miereg-standard]]
 .Standard portion (bits 15:0) of `mie`.
-include::images/bytefield/miereg-standard.adoc[]
+include::images/bytefield/miereg-standard.edn[]
+endif::[]
 
 [{ohg-config}]
 Bits `mip`.MEIP and `mie`.MEIE are the interrupt-pending and
@@ -2156,7 +2157,7 @@ endif::[]
 
 ifdef::archi-default,RVZsmcntrpmf-true[]
 .Hardware performance monitor counters.
-include::images/bytefield/hpmevents.adoc[]
+include::images/bytefield/hpmevents.edn[]
 
 The `mhpmcounters` are *WARL* registers that support up to 64 bits of
 precision on RV32 and RV64.
@@ -2190,7 +2191,7 @@ these events is defined by the platform, but event 0 is defined to mean
 selector are read-only 0.
 
 .Hardware performance monitor counters.
-include::images/bytefield/hpmevents.adoc[]
+include::images/bytefield/hpmevents.edn[]
 endif::[]
 
 The `mhpmcounters` are *WARL* registers that support up to 64 bits of
@@ -2224,7 +2225,7 @@ counters to the next-lower privileged mode.
 
 ifdef::archi-default,RVU-true[]
 .Counter-enable (`mcounteren`) register.
-include::images/bytefield/counteren.adoc[]
+include::images/bytefield/counteren.edn[]
 
 The settings in this register only control accessibility. The act of
 reading or writing this register does not affect the underlying
@@ -2285,7 +2286,7 @@ endif::[]
 ==== Machine Counter-Inhibit (`mcountinhibit`) Register
 
 .Counter-inhibit `mcountinhibit` register
-include::images/bytefield/counterinh.adoc[]
+include::images/bytefield/counterinh.edn[]
 
 ifdef::archi-default,RVZsmcntrpmf-true[]
 The counter-inhibit register `mcountinhibit` is a 32-bit *WARL* register that
@@ -2333,7 +2334,7 @@ machine-mode hart-local context space and swapped with a user register
 upon entry to an M-mode trap handler.
 
 .Machine-mode scratch register.
-include::images/bytefield/mscratch.adoc[]
+include::images/bytefield/mscratch.edn[]
 
 ifeval::[{note} == true]
 [NOTE]
@@ -2394,7 +2395,7 @@ though it may be explicitly written by software.
 
 [[mepcreg]]
 .Machine exception program counter register.
-include::images/bytefield/mepcreg.adoc[]
+include::images/bytefield/mepcreg.edn[]
 
 [[mcause]]
 ==== Machine Cause (`mcause`) Register
@@ -2413,7 +2414,7 @@ the possible machine-level exception codes. The Exception Code is a
 
 [[mcausereg]]
 .Machine Cause (`mcause`) register.
-include::images/bytefield/mcausereg.adoc[]
+include::images/bytefield/mcausereg.edn[]
 
 ifdef::archi-default,RVU-true[]
 Note that load and load-reserved instructions generate load exceptions,
@@ -2539,6 +2540,9 @@ _Designated for platform use_
 0 +
 0 +
 0 +
+0 +
+0 +
+0 +
 0
 |0 +
 1 +
@@ -2722,7 +2726,7 @@ particularly those with hardware page-table walkers.
 
 [[mtvalreg]]
 .Machine Trap Value (`mtval`) register.
-include::images/bytefield/mtvalreg.adoc[]
+include::images/bytefield/mtvalreg.edn[]
 
 
 If `mtval` is written with a nonzero value when a misaligned load or
@@ -2815,7 +2819,7 @@ and their configuration.
 
 [[mconfigptrreg]]
 .Machine Configuration Pointer (`mconfigptr`) register.
-include::images/bytefield/mconfigptrreg.adoc[]
+include::images/bytefield/mconfigptrreg.edn[]
 
 
 The pointer alignment in bits must be no smaller than MXLEN:
@@ -2863,7 +2867,7 @@ privileged than M.
 
 [[menvcfgreg]]
 .Machine environment configuration (`menvcfg`) register.
-include::images/wavedrom/menvcfgreg.adoc[]
+include::images/wavedrom/menvcfgreg.edn[]
 
 
 If bit FIOM (Fence of I/O implies Memory) is set to one in `menvcfg`,
@@ -3001,9 +3005,7 @@ ifdef::archi-CVA6+RVU-true[]
 endif::[]
 
 ifdef::archi-default,RVU-true[]
-The definition of the PMM field will be furnished by the forthcoming
+The definition of the PMM field is furnished by the Smnpm extension.
-Smnpm extension. Its allocation within `menvcfg` may change prior to the
-ratification of that extension.
 endif::[]
 
 ifdef::archi-CVA6+RVU-true[]
@@ -3076,19 +3078,15 @@ shown in <<mseccfg>>, that controls security features.
 
 [[mseccfg]]
 .Machine security configuration (`mseccfg`) register.
-include::images/wavedrom/mseccfg.adoc[]
+include::images/wavedrom/mseccfg.edn[]
 
-The definitions of the SSEED and USEED fields will be furnished by the
+The definitions of the SSEED and USEED fields are furnished by the
-forthcoming entropy-source extension, Zkr. Their allocations within
+entropy-source extension, Zkr.
-`mseccfg` may change prior to the ratification of that extension.
 
-The definitions of the RLB, MMWP, and MML fields will be furnished by
+The definitions of the RLB, MMWP, and MML fields are furnished by the
-the forthcoming PMP-enhancement extension, Smepmp. Their allocations
+PMP-enhancement extension, Smepmp.
-within `mseccfg` may change prior to the ratification of that extension.
 
-The definition of the PMM field will be furnished by the forthcoming
+The definition of the PMM field is furnished by the Smmpm extension.
-Smmpm extension. Its allocation within `mseccfg` may change prior to the
-ratification of that extension.
 
 The Zicfilp extension adds the `MLPE` field in `mseccfg`. When `MLPE` field is
 1, Zicfilp extension is enabled in M-mode. When the `MLPE` field is 0, the
@@ -3141,10 +3139,10 @@ writing `mtimecmp`). The interrupt will only be taken if interrupts are
 enabled and the MTIE bit is set in the `mie` register.
 
 .Machine time register (memory-mapped control register).
-include::images/bytefield/mtime.adoc[]
+include::images/bytefield/mtime.edn[]
 
 .Machine time compare register (memory-mapped control register).
-include::images/bytefield/mtimecmp.adoc[]
+include::images/bytefield/mtimecmp.edn[]
 
 ifeval::[{note} == true]
 [NOTE]
@@ -3228,7 +3226,7 @@ endif::[]
 
 ==== Environment Call and Breakpoint
 
-include::images/wavedrom/mm-env-call.adoc[]
+include::images/wavedrom/mm-env-call.edn[]
 
 ifdef::archi-default,RVU-true[]
 The ECALL instruction is used to make a request to the supporting
@@ -3281,7 +3279,7 @@ not increment the `minstret` CSR.
 Instructions to return from trap are encoded under the PRIV minor
 opcode.
 
-include::images/wavedrom/trap-return.adoc[]
+include::images/wavedrom/trap-return.edn[]
 
 ifdef::archi-default,RVU-true[]
 To return after handling a trap, there are separate trap return
@@ -3349,7 +3347,7 @@ cannot raise an illegal-instruction exception because TW=0 in `mstatus`, as
 described in <<virt-control>>.
 endif::[]
 
-include::images/wavedrom/wfi.adoc[]
+include::images/wavedrom/wfi.edn[]
 
 If an enabled interrupt is present or later becomes present while the
 hart is stalled, the interrupt trap will be taken on the following
@@ -3444,7 +3442,7 @@ minimum required privilege mode, as do other SYSTEM instructions.
 
 [[customsys]]
 .SYSTEM instruction encodings designated for custom use.
-include::images/bytefield/cust-sys-instr.adoc[]
+include::images/bytefield/cust-sys-instr.edn[]
 
 [[reset]]
 === Reset
@@ -3463,7 +3461,9 @@ the platform mandates a different reset value for some PMP registers’ A
 and L fields. If the hypervisor extension is implemented, the
 `hgatp`.MODE and `vsatp`.MODE fields are reset to 0. If the Smrnmi
 extension is implemented, the `mnstatus`.NMIE field is reset to 0. No
- *WARL* field contains an illegal value. All other hart state is UNSPECIFIED.
+ *WARL* field contains an illegal value. If the Zicfilp extension is
+implemented, the `mseccfg`.MLPE field is reset to 0. All other hart
+state is UNSPECIFIED.
 
 The `mcause` values after reset have implementation-specific
 interpretation, but the value 0 should be returned on implementations
@@ -3817,7 +3817,7 @@ Specific supported values for this PMA are represented by MAG__NN__, e.g.,
 MAG16 indicates the misaligned atomicity granule is at least 16 bytes.
 
 The misaligned atomicity granule PMA applies only to AMOs, loads and stores
-defined in the base ISAs, and loads and stores of no more than MXLEN bits
+defined in the base ISAs, and loads and stores of no more than XLEN bits
 defined in the F, D, and Q extensions.
 For an instruction in that set, if all accessed bytes lie within the same
 misaligned atomicity granule, the instruction will not raise an exception for
@@ -4145,11 +4145,11 @@ endif::[]
 ifdef::archi-default[]
 [[pmpcfg-rv32]]
 .RV32 PMP configuration CSR layout.
-include::images/bytefield/pmp-rv32.adoc[]
+include::images/bytefield/pmp-rv32.edn[]
 
 [[pmpcfg-rv64]]
 .RV64 PMP configuration CSR layout.
-include::images/bytefield/pmp-rv64.adoc[]
+include::images/bytefield/pmp-rv64.edn[]
 
 
 The PMP address registers are CSRs named `pmpaddr0`-`pmpaddr63`. Each
@@ -4177,11 +4177,11 @@ endif::[]
 ifdef::archi-default[]
 [[pmpaddr-rv32]]
 .PMP address register format, RV32.
-include::images/bytefield/pmpaddr-rv32.adoc[]
+include::images/bytefield/pmpaddr-rv32.edn[]
 
 [[pmpaddr-rv64]]
 .PMP address register format, RV64.
-include::images/bytefield/pmpaddr-rv64.adoc[]
+include::images/bytefield/pmpaddr-rv64.edn[]
 endif::[]
 
 ifdef::archi-CVA6[]
@@ -4201,7 +4201,7 @@ The 14 upper PMP configuration CSRs, `pmpcfg2`-`pmpcfg15`, are read-only zero.
 
 [[pmpcfg-rv32]]
 .RV32 PMP configuration CSR layout.
-include::images/bytefield/pmp-rv32.adoc[]
+include::images/bytefield/pmp-rv32.edn[]
 
 [{ohg-config}] The PMP address registers are CSRs named `pmpaddr0`-`pmpaddr63`. Each
 PMP address register encodes bits 33-2 of a 34-bit physical address for
@@ -4212,7 +4212,7 @@ The 56 upper PMP address CSRs, `pmpaddr8`-`pmpaddr63`, are read-only zero.
 
 [[pmpaddr-rv32]]
 .PMP address register format, RV32.
-include::images/bytefield/pmpaddr-rv32.adoc[]
+include::images/bytefield/pmpaddr-rv32.edn[]
 endif::[]
 
 <<pmpcfg>> shows the layout of a PMP configuration
@@ -4223,7 +4223,7 @@ W, and X fields form a collective *WARL* field for which the combinations with R
 
 [[pmpcfg]]
 .PMP configuration register format.
-include::images/bytefield/pmpcfg.adoc[]
+include::images/bytefield/pmpcfg.edn[]
 
 
 Attempting to fetch an instruction from a PMP region that does not have
@@ -4240,7 +4240,6 @@ access-fault exception.
 The A field in a PMP entry's configuration register encodes the
 address-matching mode of the associated PMP address register. The
 encoding of this field is shown in <<pmpcfg-a>>.
-
 When A=0, this PMP entry is disabled and matches no addresses. Two other
 address-matching modes are supported: naturally aligned power-of-2
 regions (NAPOT), including the special case of naturally aligned

docs/riscv-isa/src/priv-preface.adoc

@@ -6,24 +6,24 @@
 This document describes the RISC-V privileged architecture tailored for
 OpenHW Group {ohg-config}.
 
-[.big]*_Preface to Version 20240801_*
+[.big]*_Preface to Version 20241017_*
 
 This document describes the RISC-V privileged architecture. This
-release, version 20240801, contains the following versions of the RISC-V ISA
+release, version 20241017, contains the following versions of the RISC-V ISA
 modules:
 
 [%autowidth,float="center",align="center",cols="^,<,^",options="header",]
 |===
 |Module |Version |Status
-|_Machine ISA_ +
+|*Machine ISA* +
 *Smstateen Extension* +
 *Smcsrind/Sscsrind Extension* +
 *Smepmp* +
 *Smcntrpmf* +
 *Smrnmi Extension* +
 *Smcdeleg* +
-_Smdbltrp_ +
+*Smdbltrp* +
-_Supervisor ISA_ +
+*Supervisor ISA* +
 *Svade Extension* +
 *Svnapot Extension* +
 *Svpbmt Extension* +
@@ -31,20 +31,22 @@ _Supervisor ISA_ +
 *Svadu Extension* +
 *Sstc* +
 *Sscofpmf* +
-_Ssdbltrp_ +
+*Ssdbltrp* +
 *Hypervisor ISA* +
-_Shlcofideleg_ +
+*Shlcofideleg* +
 *Svvptc*
 
-|_1.13_ +
+|*1.13* +
-*1.0* +
+*1.0* +
-*1.0* +
+*1.0* +
-*1.0* +
+*1.0* +
-*1.0* +
+*1.0* +
-*1.0* +
+*1.0* +
-*1.0* +
+*1.0* +
-_1.0_ +
+*1.0* +
-_1.13_ +
+*1.13* +
+*1.0* +
+*1.0* +
 *1.0* +
 *1.0* +
 *1.0* +
@@ -52,20 +54,20 @@ _1.13_ +
 *1.0* +
 *1.0* +
 *1.0* +
-_1.0_ +
 *1.0* +
-_0.1_ +
 *1.0*
 
-|_Draft_ +
+|*Ratified* +
-*Ratified* +
+*Ratified* +
-*Ratified* +
+*Ratified* +
-*Ratified* +
+*Ratified* +
-*Ratified* +
+*Ratified* +
-*Ratified* +
+*Ratified* +
-*Ratified* +
+*Ratified* +
-_Draft_ +
+*Ratified* +
-_Draft_ +
+*Ratified* +
+*Ratified* +
+*Ratified* +
 *Ratified* +
 *Ratified* +
 *Ratified* +
@@ -73,9 +75,7 @@ _Draft_ +
 *Ratified* +
 *Ratified* +
 *Ratified* +
-_Draft_ +
 *Ratified* +
-_Draft_ +
 *Ratified*
 |===
 

docs/riscv-isa/src/riscv-privileged.adoc

@@ -4,8 +4,8 @@ include::config.adoc[]
 = The RISC-V Instruction Set Manual for {ohg-config}: Volume II: Privileged Architecture
 include::../docs-resources/global-config.adoc[]
 :description: Volume II - Privileged Architecture
-:revnumber: 20240801
+:revnumber: 20241017
-//:revremark: Pre-release version
+:revremark: This document is in Ratified state.
 //development: assume everything can change
 //stable: assume everything could change
 //frozen: of you implement this version you assume the risk that something might change because of the public review cycle  but we expect little to no change.
@@ -15,7 +15,7 @@ include::../docs-resources/global-config.adoc[]
 :appendix-caption: Appendix
 :imagesdir: ../docs-resources/images
 :title-logo-image: image:risc-v_logo.png["RISC-V International Logo",pdfwidth=3.25in,align=center]
-:page-background-image: image:draft.png[opacity=20%]
+//:page-background-image: image:draft.png[opacity=20%]
 :title-page-background-image: image:ohg_logo.png[fit=none,pdfwidth=3.25in,position=top]
 //:title-page-background-image: none
 //:back-cover-image: image:backpage.png[opacity=25%]
@@ -70,11 +70,11 @@ Avižienis, Jacob Bachmeyer, Allen J. Baum, Jonathan Behrens, Paolo Bonzini, Rus
 Christopher Celio, Chuanhua Chang, David Chisnall, Anthony Coulter, Palmer Dabbelt, Monte
 Dalrymple, Paul Donahue, Greg Favor, Dennis Ferguson,  Marc Gauthier, Andy Glew,
 Gary Guo, Mike Frysinger, John Hauser, David Horner, Olof
-Johansson, David Kruckemyer, Yunsup Lee, Daniel Lustig, Andrew Lutomirski, Prashanth Mundkur,
+Johansson, David Kruckemyer, Yunsup Lee, Daniel Lustig, Andrew Lutomirski, Martin Maas, Prashanth Mundkur,
 Jonathan Neuschäfer, Rishiyur
 Nikhil, Stefan O'Rear, Albert Ou, John Ousterhout, David Patterson, Dmitri
 Pavlov, Kade Phillips, Josh Scheid, Colin Schmidt, Michael Taylor, Wesley Terpstra, Matt Thomas, Tommy Thorn, Ray
-VanDeWalker, Megan Wachs, Steve Wallach, Andrew Waterman, Claire Wolf,
+VanDeWalker, Megan Wachs, Steve Wallach, Andrew Waterman, Claire Wolf, Adam Zabrocki,
 and Reinoud Zandijk.._
 
 _This document is released under a Creative Commons Attribution 4.0 International License._
@@ -106,6 +106,7 @@ include::sscofpmf.adoc[]
 include::hypervisor.adoc[]
 include::priv-cfi.adoc[]
 include::ssdbltrp.adoc[]
+include::zpm.adoc[]
 include::priv-insns.adoc[]
 include::priv-history.adoc[]
 include::bibliography.adoc[]

docs/riscv-isa/src/riscv-unprivileged.adoc

@@ -4,7 +4,7 @@ include::config.adoc[]
 = The RISC-V Instruction Set Manual for {ohg-config}: Volume I - Unprivileged Architecture
 include::../docs-resources/global-config.adoc[]
 :description: Unprivileged Architecture
-:revnumber: 20240801
+:revnumber: 20241017
 //:revremark: Pre-release version
 :colophon:
 :preface-title: Preamble
@@ -30,6 +30,7 @@ include::../docs-resources/global-config.adoc[]
 :example-caption: Example
 :listing-caption: Listing
 :sectnums:
+:sectnumlevels: 5
 :toc: left
 :toclevels: 5
 :source-highlighter: pygments
@@ -197,7 +198,6 @@ include::zfinx.adoc[]
 include::c-st-ext.adoc[]
 include::zc.adoc[]
 include::b-st-ext.adoc[]
-include::j-st-ext.adoc[]
 include::p-st-ext.adoc[]
 include::v-st-ext.adoc[]
 include::scalar-crypto.adoc[]

docs/riscv-isa/src/rv64.adoc

@@ -46,7 +46,7 @@ endif::[]
 
 ==== Integer Register-Immediate Instructions
 
-include::images/wavedrom/rv64i-base-int.adoc[]
+include::images/wavedrom/rv64i-base-int.edn[]
 [[rv64i-base-int]]
 //.RV64I register-immediate instructions
 
@@ -57,7 +57,7 @@ immediate to register _rs1_ and produces the proper sign extension of a
 writes the sign extension of the lower 32 bits of register _rs1_ into
 register _rd_ (assembler pseudoinstruction SEXT.W).
 
-include::images/wavedrom/rv64i-slli.adoc[]
+include::images/wavedrom/rv64i-slli.edn[]
 [[rv64i-slli]]
 //.RV64I register-immediate (descr ADDIW) instructions
 
@@ -74,7 +74,7 @@ copied into the vacated upper bits).
 (((RV64I, SRLIW)))
 (((RV64I, RV64I-only)))
 
-include::images/wavedrom/rv64i-slliw.adoc[]
+include::images/wavedrom/rv64i-slliw.edn[]
 [[rv64i-slliw]]
 
 SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously
@@ -91,7 +91,7 @@ are marked as reserved. This is a backwards-compatible change.
 ====
 endif::[]
 
-include::images/wavedrom/rv64_lui-auipc.adoc[]
+include::images/wavedrom/rv64-lui-auipc.edn[]
 [[rv64_lui-auipc]]
 //.RV64I register-immediate (descr) instructions
 
@@ -119,7 +119,7 @@ endif::[]
 ==== Integer Register-Register Operations
 
 //this diagramdoesn't match the tex specification
-include::images/wavedrom/rv64i_int-reg-reg.adoc[]
+include::images/wavedrom/rv64i-int-reg-reg.edn[]
 [[int_reg-reg]]
 //.RV64I integer register-register instructions
 
@@ -147,7 +147,7 @@ results to 64 bits. The shift amount is given by _rs2[4:0]_.
 RV64I extends the address space to 64 bits. The execution environment
 will define what portions of the address space are legal to access.
 
-include::images/wavedrom/load_store.adoc[]
+include::images/wavedrom/load-store.edn[]
 [[load_store]]
 //.Load and store instructions
 

docs/riscv-isa/src/supervisor.adoc

@@ -908,17 +908,12 @@ enabled.
 endif::[]
 
 ifdef::archi-default[]
-The definition of the CBZE field will be furnished by the forthcoming
+The definition of the CBZE field is furnished by the Zicboz extension.
-Zicboz extension. Its allocation within `senvcfg` may change prior to
-the ratification of that extension.
 
-The definitions of the CBCFE and CBIE fields will be furnished by the
+The definitions of the CBCFE and CBIE fields are furnished by the Zicbom
-forthcoming Zicbom extension. Their allocations within `senvcfg` may
+extension.
-change prior to the ratification of that extension.
 
-The definition of the PMM field will be furnished by the forthcoming
+The definition of the PMM field is furnished by the Ssnpm extension.
-Ssnpm extension. Its allocation within `senvcfg` may change prior to the
-ratification of that extension.
 
 The Zicfilp extension adds the `LPE` field in `senvcfg`. When the `LPE` field is
 set to 1, the Zicfilp extension is enabled in VU/U-mode. When the `LPE` field is
@@ -1646,8 +1641,9 @@ Two schemes to manage the A and D bits are defined:
   architecturally. However, updates to the D bit, resulting from an
   explicit store, must be exact (i.e., non-speculative), and observed in
   program order by the local hart. When two-stage address translation is
-  active, updates of the D bit in G-stage PTEs may be performed as a
+  active, updates to the D bit in G-stage PTEs may be performed by an
-  result of speculative updates of the A bit in VS-stage PTEs.          +
+  implicit access to a VS-stage PTE, if the G-stage PTE provides write
+  permission, before any speculative access to the VS-stage PTE.        +
                                                                         +
   The PTE update must appear in the global memory order before the
   memory access that caused the PTE update and before any subsequent
@@ -2478,6 +2474,11 @@ Second, if `vsatp`.MODE is not equal to zero, non-zero VS-stage PTE PBMT
 bits override the intermediate attributes to produce the final set of
 attributes used by accesses to the page in question. Otherwise, the
 intermediate attributes are used as the final set of attributes.
+
+NOTE: These final attributes apply to implicit and explicit accesses that
+are subject to both stages of address translation.
+For accesses that are not subject to the first stage of address translation,
+e.g. VS-stage page-table accesses, the intermediate attributes apply instead.
 endif::[]
 
 ifdef::archi-default[]

docs/riscv-isa/src/zpm.adoc

@@ -0,0 +1,6 @@
+[[Zpm]]
+== Pointer Masking Extensions, Version 1.0.0
+
+ifeval::[{RVZpm} == false]
+{ohg-config}: These extensions are not supported.
+endif::[]