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https://github.com/openhwgroup/cva6.git
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Implement hardware break-points
This commit is contained in:
Florian Zaruba
parent
b352a55106
commit
67b97d12da
2 changed files with 123 additions and 61 deletions
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@ -311,25 +311,12 @@ package ariane_pkg;
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DBG_HIT = 15'h4,
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DBG_IE = 15'h8,
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DBG_CAUSE = 15'hC,
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DBG_BPCTRL0 = 15'h40,
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DBG_BPDATA0 = 15'h44,
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DBG_BPCTRL1 = 15'h48,
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DBG_BPDATA1 = 15'h4C,
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DBG_BPCTRL2 = 15'h50,
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DBG_BPDATA2 = 15'h54,
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DBG_BPCTRL3 = 15'h58,
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DBG_BPDATA3 = 15'h5C,
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DBG_BPCTRL4 = 15'h60,
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DBG_BPDATA4 = 15'h64,
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DBG_BPCTRL5 = 15'h68,
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DBG_BPDATA5 = 15'h6C,
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DBG_BPCTRL6 = 15'h70,
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DBG_BPDATA6 = 15'h74,
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DBG_BPCTRL7 = 15'h78,
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DBG_BPDATA7 = 15'h7C,
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DBG_GPR = 15'h4xx,
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DBG_CSR = 15'h5xx,
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DBG_BPCTRL = 15'b????000,
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DBG_BPDATA = 15'b?????00,
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DBG_GPR = 15'h4??,
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DBG_CSR = 15'h5??,
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DBG_NPC = 15'h2000,
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DBG_PPC = 15'h2004
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} debug_reg_t;
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endpackage
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@ -39,6 +39,10 @@ module debug_unit (
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output logic debug_csr_we_o,
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output logic [63:0] debug_csr_wdata_o,
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input logic [63:0] debug_csr_rdata_i,
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// CPU Control
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output logic [63:0] debug_pc_o,
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output logic debug_set_pc_o,
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// HWPB
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// External Debug Interface
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input logic debug_req_i,
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output logic debug_gnt_o,
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@ -59,7 +63,7 @@ module debug_unit (
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logic rvalid_n, rvalid_q;
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logic rdata_n, rdata_q;
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// save previous PC
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logic ppc_n, ppc_q;
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logic dbg_ppc_n, dbg_ppc_q;
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// ---------------
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// Debug Register
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// ---------------
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@ -69,15 +73,21 @@ module debug_unit (
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logic [63:0] dbg_cause_n, dbg_cause_q;
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// single step mode
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logic dbg_ss_n, dbg_ss_q;
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logic dbg_ssth_n, dbg_ssth_q;
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logic [63:0] dbg_hit_n, dbg_hit_q;
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// hardware breakpoints
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logic [7:0][3:0] dbg_hwbp_ctrl_n, dbg_hwbp_ctrl_q;
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logic [7:0][63:0] dbg_hwbp_data_n, dbg_hwbp_data_q;
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// ----------------------
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// Debug Control Signals
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// ----------------------
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// change debug mode
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logic halt_req, resume_req;
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logic stepped_single;
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// assigns, we can output a couple of signals directly
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assign debug_rvalid_o = rvalid_q;
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assign debug_rdata_o = rdata_q;
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assign debug_halted_o = (CS == HALTED);
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// | Address | Name | Description |
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// |---------------|-----------------|---------------------------------------------------------------------|
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// | 0x0000-0x007F | Debug Registers | Always accessible, even when the core is running |
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@ -85,20 +95,21 @@ module debug_unit (
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// | 0x0500-0x05FF | FPR (f0-f31) | Reserved. Not used in the Ariane. |
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// | 0x2000-0x20FF | Debug Registers | Only accessible if the core is halted |
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// | 0x4000-0x7FFF | CSR | Control and Status Registers. Only accessible if the core is halted |
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always_comb begin : debug_ctrl
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debug_gnt_o = 1'b0;
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rdata_n = 'b0;
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rvalid_n = 1'b0;
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debug_gnt_o = 1'b0;
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rdata_n = 'b0;
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rvalid_n = 1'b0;
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halt_req = 1'b0;
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halt_req = 1'b0;
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// update the previous PC if got a valid commit
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ppc_n = (commit_ack_i) ? commit_instr_i.pc : ppc_q;
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dbg_ppc_n = (commit_ack_i) ? commit_instr_i.pc : dbg_ppc_q;
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// debug registers
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dbg_ie_n = dbg_ie_q;
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dbg_cause_n = dbg_cause_q;
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dbg_ss_n = dbg_ss_q;
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dbg_ssth_n = dbg_ssth_q;
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dbg_ie_n = dbg_ie_q;
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dbg_cause_n = dbg_cause_q;
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dbg_ss_n = dbg_ss_q;
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dbg_hit_n = dbg_hit_q;
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dbg_hwbp_ctrl_n = dbg_hwbp_ctrl_q;
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dbg_hwbp_data_n = dbg_hwbp_data_q;
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// GPR defaults
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debug_gpr_req_o = 1'b0;
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debug_gpr_addr_o = debug_addr_i[6:2];
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@ -109,9 +120,13 @@ module debug_unit (
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debug_csr_addr_o = debug_addr_i[13:2];
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debug_csr_we_o = 1'b0;
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debug_csr_wdata_o = 64'b0;
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// change ctrl flow
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debug_pc_o = 64'b0;
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debug_set_pc_o = 1'b0;
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// we did one single step, set the sticky bit
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if (stepped_single)
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dbg_ssth_n = 1'b1;
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dbg_hit_n = 1'b1;
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// ----------
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// Read
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@ -121,13 +136,24 @@ module debug_unit (
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// we can immediately grant the request
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debug_gnt_o = 1'b1;
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// decode debug address
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casex (debug_addr_i)
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DBG_CTRL: rdata_n = {32'b0, 15'b0, debug_halted_o, 15'b0, dbg_ss_q};
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DBG_HIT: rdata_n = {63'b0, dbg_ssth_q};
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DBG_IE: rdata_n = dbg_ie_q;
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DBG_CAUSE: rdata_n = dbg_cause_q;
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DBG_NPC: rdata_n = commit_instr_i.pc;
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DBG_PPC: rdata_n = ppc_q;
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casez (debug_addr_i)
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DBG_CTRL: rdata_n = {32'b0, 15'b0, debug_halted_o, 15'b0, dbg_ss_q};
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DBG_HIT: rdata_n = {63'b0, dbg_hit_q};
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DBG_IE: rdata_n = dbg_ie_q;
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DBG_CAUSE: rdata_n = dbg_cause_q;
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// all breakpoints are implemented
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DBG_BPCTRL: rdata_n = {57'b0, dbg_hwbp_ctrl_q[debug_addr_i[5:3]], 2'b0, 1'b1};
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DBG_BPDATA: rdata_n = dbg_hwbp_data_q[debug_addr_i[5:3]];
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DBG_NPC: begin
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if (debug_halted_o)
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rdata_n = commit_instr_i.pc;
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end
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DBG_PPC: begin
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if (debug_halted_o)
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rdata_n = dbg_ppc_q;
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end
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DBG_GPR: begin
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if (debug_halted_o) begin
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@ -151,7 +177,7 @@ module debug_unit (
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// we can also immediately grant
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debug_gnt_o = 1'b1;
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// decode debug address
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case (debug_addr_i)
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casez (debug_addr_i)
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DBG_CTRL: begin
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// check if requested a halt
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halt_req = debug_wdata_i[16];
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@ -159,10 +185,22 @@ module debug_unit (
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// enable/disable single step
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dbg_ss_n = debug_wdata_i[0];
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end
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DBG_HIT: dbg_ssth_n = debug_wdata_i[0];
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DBG_IE: dbg_ie_n = debug_wdata_i;
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DBG_HIT: dbg_hit_n = {debug_wdata_i[15:8], debug_wdata_i[0]};
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DBG_IE: dbg_ie_n = debug_wdata_i;
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DBG_CAUSE: dbg_cause_n = debug_wdata_i;
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// Only triggering on instruction fetch is allowed at the moment
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DBG_BPCTRL: dbg_hwbp_ctrl_n[debug_addr_i[5:3]] = {3'b0, debug_wdata_i[1]};
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DBG_BPDATA: dbg_hwbp_data_n[debug_addr_i[5:3]] = debug_wdata_i;
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DBG_NPC: begin
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// Change CTRL Flow to debug PC
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debug_pc_o = debug_wdata_i;
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debug_set_pc_o = 1'b1;
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end
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// PPC is read-only
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DBG_PPC:;
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DBG_GPR: begin
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if (debug_halted_o) begin
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debug_gpr_req_o = 1'b1;
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@ -187,12 +225,22 @@ module debug_unit (
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// save the cause why we entered the exception
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dbg_cause_n = ex_i.cause;
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end
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// --------------------
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// HW Breakpoints
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// --------------------
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// check all possible breakpoints
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for (logic [7:0] i = 0; i < 8; i++) begin
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// check if a breakpoint is triggering, therefore check if it is enabled
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if (dbg_hwbp_ctrl_q[1]) begin
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// check if the PC is matching and the processor is currently retiring the instruction
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if (commit_instr_i.pc == dbg_hwbp_data_q && commit_ack_i) begin
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halt_req = 1'b1;
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dbg_hit_n[15:8] = i;
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end
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end
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end
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end
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// --------------------
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// HW Breakpoints
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// --------------------
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// --------------------
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// Stall Control
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// --------------------
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@ -204,7 +252,9 @@ module debug_unit (
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case (CS)
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// CPU is running normally
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RUNNING: begin
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// external debugger requested to halt the CPU
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// 1. external debugger requested to halt the CPU
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// 2. cross-trigger requested a halt
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// 3. a break-point hit
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if (halt_req || debug_halt_i) begin
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NS = HALT_REQ;
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end
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@ -236,7 +286,7 @@ module debug_unit (
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NS = RUNNING;
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// resume from single step, check if single stepping is enabled and if the sticky bit is cleared
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if (dbg_ss_q && !dbg_ssth_q) begin
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if (dbg_ss_q && !dbg_hit_q) begin
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NS = SINGLE_STEP;
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end
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end
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@ -249,19 +299,44 @@ module debug_unit (
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// --------------------
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (~rst_ni) begin
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CS <= RUNNING;
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rdata_q <= '0;
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rvalid_q <= 1'b0;
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ppc_q <= 64'b0;
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dbg_ie_q <= 64'b0;
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dbg_cause_q <= 64'b0;
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CS <= RUNNING;
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rdata_q <= '0;
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rvalid_q <= 1'b0;
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dbg_ppc_q <= 64'b0;
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dbg_ie_q <= 64'b0;
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dbg_cause_q <= 64'b0;
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dbg_hwbp_ctrl_q <= '0;
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dbg_hwbp_data_q <= '0;
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dbg_ss_q <= 1'b0;
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dbg_hit_q <= 1'b0;
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end else begin
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CS <= NS;
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rdata_q <= rdata_n;
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rvalid_q <= rvalid_n;
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ppc_q <= ppc_n;
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dbg_ie_q <= dbg_ie_n;
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dbg_cause_q <= dbg_cause_n;
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CS <= NS;
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rdata_q <= rdata_n;
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rvalid_q <= rvalid_n;
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dbg_ppc_q <= dbg_ppc_n;
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dbg_ie_q <= dbg_ie_n;
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dbg_cause_q <= dbg_cause_n;
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dbg_ss_q <= dbg_ss_n;
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dbg_hit_q <= dbg_hit_n;
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dbg_hwbp_ctrl_q <= dbg_hwbp_ctrl_n;
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dbg_hwbp_data_q <= dbg_hwbp_data_n;
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end
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end
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//--------------
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// Assertions
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//--------------
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// check that no registers are accessed when we are not in debug mode
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assert property (
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@(posedge clk_i) (debug_req_i) |-> ((debug_halted_o == 1'b1) ||
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((debug_addr_i[14] != 1'b1) &&
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(debug_addr_i[13:7] != 5'b0_1001) &&
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(debug_addr_i[13:7] != 5'b0_1000)) ) )
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else $warning("Trying to access internal debug registers while core is not stalled");
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// check that all accesses are word-aligned
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assert property (
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@(posedge clk_i) (debug_req_i) |-> (debug_addr_i[1:0] == 2'b00) );
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endmodule
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