Fixed double cycle bug in driver + reset seq

tb/agents/fu_if/fu_if_driver.svh

@@ -29,25 +29,25 @@ endfunction
 
 task fu_if_driver::run_phase(uvm_phase phase);
     fu_if_seq_item cmd;
-
+    fork
     forever begin : cmd_loop
         shortint unsigned result;
-        seq_item_port.get_next_item(cmd);
 
         // using clocking blocks this is possible
-        @(posedge fu.sck)
+	seq_item_port.get_next_item(cmd);
+
         fu.sck.operand_a <= cmd.operand_a;
         fu.sck.operand_b <= cmd.operand_b;
         fu.sck.operand_c <= cmd.operand_c;
         fu.sck.operator <= cmd.operator;
-
-        @(negedge fu.sck) 
+	@(fu.sck)
 	cmd.result = fu.sck.result;
         cmd.compare_result = fu.sck.comparison_result;
 
         seq_item_port.item_done();
 
     end : cmd_loop
+    join_none
 endtask : run_phase
 
 function void fu_if_driver::build_phase(uvm_phase phase);

tb/alu_tb.sv

@@ -55,7 +55,7 @@ module alu_tb;
     initial begin
         // print the topology
         uvm_top.enable_print_topology = 1;
-        // Start UVM test
+	// Start UVM test
         run_test();
     end
 endmodule

tb/sequences/alu_sequence_pkg.sv

@@ -6,5 +6,5 @@ import uvm_pkg::*;
 
 `include "uvm_macros.svh"
 `include "fibonacci_sequence.svh"
-
+`include "reset_sequence.svh"
 endpackage

tb/sequences/reset_sequence.svh

@@ -0,0 +1,27 @@
+class reset_sequence extends fu_if_seq;
+
+   `uvm_object_utils(reset_sequence);
+
+   function new(string name = "reset");
+      super.new(name);
+   endfunction : new
+
+
+   task body();
+      
+      fu_if_seq_item command;
+
+      command = fu_if_seq_item::type_id::create("command");
+      `uvm_info("RESET", "Starting reset phase", UVM_MEDIUM);
+      // reset 
+      for (int i = 0; i < 20; i++) begin
+      start_item(command);
+      command.operand_a = 0;
+      command.operand_b = 0;
+      command.operand_c = 0;
+      command.operator = 7'b00;
+      finish_item(command);
+      end
+
+   endtask : body
+endclass : reset_sequence

tb/test/alu_test.svh

@@ -31,6 +31,7 @@ endfunction
 task alu_test::run_phase(uvm_phase phase);
     phase.raise_objection(this, "alu_test");
     //fibonacci_sequence fibonacci;
+    super.run_phase(phase);
     fibonacci = new("fibonacci");
     fibonacci.start(sequencer_h);    
     // Testlogic goes here

tb/test/alu_test_base.svh

@@ -22,6 +22,7 @@ class alu_test_base extends uvm_test;
     alu_env m_env;
     fu_if_sequencer sequencer_h;
 
+    reset_sequence reset;
     // ---------------------
     // Agent configuration
     // ---------------------
@@ -36,6 +37,7 @@ class alu_test_base extends uvm_test;
     extern function new(string name = "alu_test_base", uvm_component parent = null);
     extern function void build_phase(uvm_phase phase);
     extern function void end_of_elaboration_phase(uvm_phase phase);
+    extern task run_phase(uvm_phase phase);
 endclass : alu_test_base
 
 function alu_test_base::new(string name = "alu_test_base", uvm_component parent = null);
@@ -68,3 +70,8 @@ endfunction
 function void alu_test_base::end_of_elaboration_phase(uvm_phase phase);
     sequencer_h = m_env.m_fu_if_sequencer;
 endfunction
+
+task alu_test_base::run_phase(uvm_phase phase);
+    reset = new("reset");
+    reset.start(sequencer_h);
+endtask