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https://github.com/openhwgroup/cva6.git
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Fix CI
This commit is contained in:
Michael Schaffner
parent
b776416a7b
commit
68d4bd1bfc
5 changed files with 27 additions and 30 deletions
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@ -41,14 +41,14 @@ build:
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run-asm-tests-questa:
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stage: test_std
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script:
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- make -j${NUM_JOBS} run-asm-tests questa_version=$QUESTASIM_VERSION
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- make -j${NUM_JOBS} run-asm-tests
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dependencies:
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- build
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run-benchmarks-questa:
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stage: test_std
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script:
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- make -j${NUM_JOBS} run-benchmarks questa_version=$QUESTASIM_VERSION
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- make -j${NUM_JOBS} run-benchmarks
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dependencies:
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- build
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@ -56,7 +56,7 @@ run-benchmarks-questa:
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run-asm-tests1-verilator:
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stage: test_std
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script:
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- make -j${NUM_JOBS} run-asm-tests1-verilator verilator=$VERILATOR_ROOT/bin/verilator
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- make -j${NUM_JOBS} run-asm-tests1-verilator
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dependencies:
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- build
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@ -64,14 +64,14 @@ run-asm-tests1-verilator:
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run-asm-tests2-verilator:
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stage: test_std
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script:
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- make -j${NUM_JOBS} run-asm-tests2-verilator verilator=$VERILATOR_ROOT/bin/verilator
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- make -j${NUM_JOBS} run-asm-tests2-verilator
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dependencies:
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- build
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run-benchmarks-verilator:
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stage: test_std
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script:
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- make -j${NUM_JOBS} run-benchmarks-verilator verilator=$VERILATOR_ROOT/bin/verilator
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- make -j${NUM_JOBS} run-benchmarks-verilator
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dependencies:
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- build
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11
.travis.yml
11
.travis.yml
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@ -67,33 +67,34 @@ jobs:
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- stage: compile2
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name: build tools
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script:
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- ci/install-verilator.sh
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- ci/install-fesvr.sh
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- ci/install-verilator.sh
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- ci/install-dtc.sh
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- ci/install-spike.sh
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- stage: test
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name: run riscv benchmarks
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script:
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- ci/build-riscv-tests.sh
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- make -j${NUM_JOBS} run-benchmarks-verilator verilator=$VERILATOR_ROOT/bin/verilator
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- make -j${NUM_JOBS} run-benchmarks-verilator
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# rv64ui-p-* tests
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- stage: test
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name: run asm tests1
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script:
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- ci/build-riscv-tests.sh
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- make -j${NUM_JOBS} run-asm-tests1-verilator verilator=$VERILATOR_ROOT/bin/verilator
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- make -j${NUM_JOBS} run-asm-tests1-verilator
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# rv64ui-v-* tests
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- stage: test
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name: run asm tests2
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script:
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- ci/build-riscv-tests.sh
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- make -j${NUM_JOBS} run-asm-tests2-verilator verilator=$VERILATOR_ROOT/bin/verilator
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- make -j${NUM_JOBS} run-asm-tests2-verilator
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- stage: test
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name: run torture
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script:
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- ci/get-torture.sh
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- make clean
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- make torture-gen
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- make torture-rtest-verilator verilator=$VERILATOR_ROOT/bin/verilator
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- make torture-rtest-verilator
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# extra time during long builds
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install: travis_wait
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12
Makefile
12
Makefile
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@ -199,7 +199,7 @@ verilate_command := $(verilator)
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--exe tb/ariane_tb.cpp tb/dpi/SimDTM.cc tb/dpi/SimJTAG.cc tb/dpi/remote_bitbang.cc
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# User Verilator, at some point in the future this will be auto-generated
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verilate: $(dpi-library)/ariane_dpi.so
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verilate:
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$(verilate_command)
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cd $(ver-library) && make -j${NUM_JOBS} -f Variane_testharness.mk
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@ -233,8 +233,8 @@ torture-rtest: build
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torture-rtest-verilator: verilate
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cd $(riscv-torture-dir) && printf "#!/bin/sh\ncd $(root-dir) && make run-torture-verilator defines=$(defines)" > call.sh && chmod +x call.sh
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cd $(riscv-torture-dir) && $(riscv-torture-bin) 'testrun/run -r ./call.sh -a output/test.S' | tee output/test-verilator.log
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make check-torture-verilator
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cd $(riscv-torture-dir) && $(riscv-torture-bin) 'testrun/run -r ./call.sh -a output/test.S' | tee output/test.log
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make check-torture
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run-torture: build
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vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles)+UVM_TESTNAME=${test_case} \
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@ -246,16 +246,12 @@ run-torture: build
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+signature=$(riscv-torture-dir)/output/test.rtlsim.sig ++$(riscv-torture-dir)/output/test ++$(target-options)
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run-torture-verilator: verilate
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$(ver-library)/Variane_testharness +max-cycles=$(max_cycles) +signature=$(riscv-torture-dir)/output/test.rtlsim.verilator.sig $(riscv-torture-dir)/output/test
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$(ver-library)/Variane_testharness +max-cycles=$(max_cycles) +signature=$(riscv-torture-dir)/output/test.rtlsim.sig $(riscv-torture-dir)/output/test
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check-torture:
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grep 'All signatures match for output/test' $(riscv-torture-dir)/output/test.log
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diff -s $(riscv-torture-dir)/output/test.spike.sig $(riscv-torture-dir)/output/test.rtlsim.sig
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check-torture-verilator:
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grep 'All signatures match for output/test' $(riscv-torture-dir)/output/test-verilator.log
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diff -s $(riscv-torture-dir)/output/test.spike.sig $(riscv-torture-dir)/output/test.rtlsim.verilator.sig
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clean:
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rm -rf $(riscv-torture-dir)/output/test*
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rm -rf $(library)/ $(dpi-library)/ $(ver-library)/
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@ -40,13 +40,13 @@ make clean
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make torture-gen
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# run asm tests on verilator
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make -j${NUM_JOBS} verilate verilator=$VERILATOR_ROOT/bin/verilator
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make -j${NUM_JOBS} run-asm-tests-verilator verilator=$VERILATOR_ROOT/bin/verilator
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make -j${NUM_JOBS} run-benchmarks-verilator verilator=$VERILATOR_ROOT/bin/verilator
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make -j${NUM_JOBS} torture-rtest-verilator verilator=$VERILATOR_ROOT/bin/verilator
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make -j${NUM_JOBS} verilate
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make -j${NUM_JOBS} run-asm-tests-verilator
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make -j${NUM_JOBS} run-benchmarks-verilator
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make -j${NUM_JOBS} torture-rtest-verilator
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# run asm tests on questa
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make -j${NUM_JOBS} build questa_version=$QUESTASIM_VERSION
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make -j${NUM_JOBS} run-asm-tests questa_version=$QUESTASIM_VERSION
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make -j${NUM_JOBS} run-benchmarks questa_version=$QUESTASIM_VERSION
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make -j${NUM_JOBS} torture-rtest questa_version=$QUESTASIM_VERSION
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make -j${NUM_JOBS} build
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make -j${NUM_JOBS} run-asm-tests
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make -j${NUM_JOBS} run-benchmarks
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make -j${NUM_JOBS} torture-rtest
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@ -40,7 +40,7 @@ make clean
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make torture-gen
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# run asm tests on verilator
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make -j${NUM_JOBS} verilate verilator=$VERILATOR_ROOT/bin/verilator
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make -j${NUM_JOBS} run-asm-tests-verilator verilator=$VERILATOR_ROOT/bin/verilator
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make -j${NUM_JOBS} run-benchmarks-verilator verilator=$VERILATOR_ROOT/bin/verilator
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make -j${NUM_JOBS} torture-rtest-verilator verilator=$VERILATOR_ROOT/bin/verilator
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make -j${NUM_JOBS} verilate
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make -j${NUM_JOBS} run-asm-tests-verilator
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make -j${NUM_JOBS} run-benchmarks-verilator
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make -j${NUM_JOBS} torture-rtest-verilator
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