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Update usage of riscv_instr_gen_tb_top as in other cores: adapt it in corev-dv to import cva6-dependent packages (#1862)
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2 changed files with 32 additions and 1 deletions
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verif/env/corev-dv/cva6-files.f
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verif/env/corev-dv/cva6-files.f
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@ -22,4 +22,4 @@ ${RISCV_DV_ROOT}/src/riscv_instr_pkg.sv
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${RISCV_DV_ROOT}/test/riscv_instr_test_pkg.sv
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${CVA6_DV_ROOT}/cva6_signature_pkg.sv
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${CVA6_DV_ROOT}/cva6_instr_test_pkg.sv
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${RISCV_DV_ROOT}/test/riscv_instr_gen_tb_top.sv
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${CVA6_DV_ROOT}/cva6_instr_gen_tb_top.sv
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31
verif/env/corev-dv/cva6_instr_gen_tb_top.sv
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verif/env/corev-dv/cva6_instr_gen_tb_top.sv
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@ -0,0 +1,31 @@
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/*
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* Copyright 2018 Google LLC
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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//-----------------------------------------------------------------------------
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// Copy/Modify version of riscv-dv/tests/riscv_instr_gen_tb_top.sv to add the
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// corev specific tests.
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//-----------------------------------------------------------------------------
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module cva6_instr_gen_tb_top;
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import uvm_pkg::*;
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import riscv_instr_test_pkg::*;
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import cva6_instr_test_pkg::*;
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initial begin
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run_test();
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end
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endmodule
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