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Merge remote-tracking branch 'iis-git/ariane_next' into ariane_next

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Michael Schaffner 2018-11-26 12:09:59 +01:00
commit 693fe335f3
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8 changed files with 68 additions and 43 deletions
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14
.gitlab-ci.yml
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@ -132,14 +132,14 @@ serdiv-quest:
s-asm-quest:
stage: serpent
script:
- make -j${NUM_JOBS} run-asm-tests defines=SERPENT_PULP+AXI64_CACHE_PORTS batch-mode=1
- make -j${NUM_JOBS} run-asm-tests defines=PITON_ARIANE+AXI64_CACHE_PORTS batch-mode=1
dependencies:
- build
s-bench-quest:
stage: serpent
script:
- make -j${NUM_JOBS} run-benchmarks defines=SERPENT_PULP+AXI64_CACHE_PORTS batch-mode=1
- make -j${NUM_JOBS} run-benchmarks defines=PITON_ARIANE+AXI64_CACHE_PORTS batch-mode=1
dependencies:
- build
@ -147,7 +147,7 @@ s-bench-quest:
s-asm1-ver:
stage: serpent
script:
- make -j${NUM_JOBS} run-asm-tests1-verilator defines=SERPENT_PULP+AXI64_CACHE_PORTS
- make -j${NUM_JOBS} run-asm-tests1-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS
dependencies:
- build
@ -155,14 +155,14 @@ s-asm1-ver:
s-asm2-ver:
stage: serpent
script:
- make -j${NUM_JOBS} run-asm-tests2-verilator defines=SERPENT_PULP+AXI64_CACHE_PORTS
- make -j${NUM_JOBS} run-asm-tests2-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS
dependencies:
- build
s-bench-ver:
stage: serpent
script:
- make -j${NUM_JOBS} run-benchmarks-verilator defines=SERPENT_PULP+AXI64_CACHE_PORTS
- make -j${NUM_JOBS} run-benchmarks-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS
dependencies:
- build
@ -187,7 +187,7 @@ s-dcache-quest:
# s-torture:
# stage: serpent
# script:
# - make torture-rtest defines=SERPENT_PULP+AXI64_CACHE_PORTS batch-mode=1
# - make torture-rtest-verilator defines=SERPENT_PULP+AXI64_CACHE_PORTS
# - make torture-rtest defines=PITON_ARIANE+AXI64_CACHE_PORTS batch-mode=1
# - make torture-rtest-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS
# dependencies:
# - build

10
.travis.yml
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@ -108,27 +108,27 @@ jobs:
name: run riscv benchmarks (serpent)
script:
- ci/build-riscv-tests.sh
- make -j${NUM_JOBS} run-benchmarks-verilator defines=SERPENT_PULP+AXI64_CACHE_PORTS
- make -j${NUM_JOBS} run-benchmarks-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS
# rv64ui-p-* tests
- stage: test
name: run asm tests1 (serpent)
script:
- ci/build-riscv-tests.sh
- make -j${NUM_JOBS} run-asm-tests1-verilator defines=SERPENT_PULP+AXI64_CACHE_PORTS
- make -j${NUM_JOBS} run-asm-tests1-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS
# rv64ui-v-* tests
- stage: test
name: run asm tests2 (serpent)
script:
- ci/build-riscv-tests.sh
- make -j${NUM_JOBS} run-asm-tests2-verilator defines=SERPENT_PULP+AXI64_CACHE_PORTS
- make -j${NUM_JOBS} run-asm-tests2-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS
- stage: test
name: run torture (serpent)
script:
- ci/get-torture.sh
- make clean
- make torture-gen defines=SERPENT_PULP+AXI64_CACHE_PORTS
- make torture-rtest-verilator defines=SERPENT_PULP+AXI64_CACHE_PORTS
- make torture-gen defines=PITON_ARIANE+AXI64_CACHE_PORTS
- make torture-rtest-verilator defines=PITON_ARIANE+AXI64_CACHE_PORTS

2
README.md
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@ -221,7 +221,7 @@ Ariane version 4.0 has preliminary support for the OpenPiton distributed cache s
The corresponding integration patches will soon be released on [OpenPiton GitHub repository](https://github.com/PrincetonUniversity/openpiton).
To activate the different cache system, compile your code with the macro `SERPENT_PULP`.
To activate the different cache system, compile your code with the macro `PITON_ARIANE`.
Note that this feature is still in Beta stage, and may hence not be completely bug-free.

69
include/ariane_pkg.sv
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@ -49,7 +49,7 @@ package ariane_pkg;
// depth of store-buffers, this needs to be a power of two
localparam int unsigned DEPTH_SPEC = 4;
`ifdef SERPENT_PULP
`ifdef PITON_ARIANE
// in this case we can use a small commit queue since we have a write buffer in the dcache
// we could in principle do without the commit queue in this case, but the timing degrades if we do that due
// to longer paths into the commit stage
@ -263,28 +263,53 @@ package ariane_pkg;
// we just use the default config of ariane
// otherwise we have to propagate the openpiton L15 configuration from l15.h
`ifdef PITON_ARIANE
// I$
localparam int unsigned ICACHE_LINE_WIDTH = `CONFIG_L1I_CACHELINE_WIDTH;
localparam int unsigned ICACHE_SET_ASSOC = `CONFIG_L1I_ASSOCIATIVITY;
localparam int unsigned ICACHE_INDEX_WIDTH = $clog2(`CONFIG_L1I_SIZE / ICACHE_SET_ASSOC);
localparam int unsigned ICACHE_TAG_WIDTH = 56 - ICACHE_INDEX_WIDTH;
// D$
localparam int unsigned DCACHE_LINE_WIDTH = `CONFIG_L1D_CACHELINE_WIDTH;
localparam int unsigned DCACHE_SET_ASSOC = `CONFIG_L1D_ASSOCIATIVITY;
localparam int unsigned DCACHE_INDEX_WIDTH = $clog2(`CONFIG_L1D_SIZE / DCACHE_SET_ASSOC);
localparam int unsigned DCACHE_TAG_WIDTH = 56 - DCACHE_INDEX_WIDTH;
`else
`ifndef CONFIG_L1I_CACHELINE_WIDTH
`define CONFIG_L1I_CACHELINE_WIDTH 128
`endif
`ifndef CONFIG_L1I_ASSOCIATIVITY
`define CONFIG_L1I_ASSOCIATIVITY 4
`endif
`ifndef CONFIG_L1I_SIZE
`define CONFIG_L1I_SIZE 16*1024
`endif
`ifndef CONFIG_L1D_CACHELINE_WIDTH
`define CONFIG_L1D_CACHELINE_WIDTH 128
`endif
`ifndef CONFIG_L1D_ASSOCIATIVITY
`define CONFIG_L1D_ASSOCIATIVITY 4
`endif
`ifndef CONFIG_L1I_SIZE
`define CONFIG_L1D_SIZE 16*1024
`endif
// I$
localparam int unsigned ICACHE_LINE_WIDTH = `CONFIG_L1I_CACHELINE_WIDTH;
localparam int unsigned ICACHE_SET_ASSOC = `CONFIG_L1I_ASSOCIATIVITY;
localparam int unsigned ICACHE_INDEX_WIDTH = $clog2(`CONFIG_L1I_SIZE / ICACHE_SET_ASSOC);
localparam int unsigned ICACHE_TAG_WIDTH = 56 - ICACHE_INDEX_WIDTH;
// D$
localparam int unsigned DCACHE_LINE_WIDTH = `CONFIG_L1D_CACHELINE_WIDTH;
localparam int unsigned DCACHE_SET_ASSOC = `CONFIG_L1D_ASSOCIATIVITY;
localparam int unsigned DCACHE_INDEX_WIDTH = $clog2(`CONFIG_L1D_SIZE / DCACHE_SET_ASSOC);
localparam int unsigned DCACHE_TAG_WIDTH = 56 - DCACHE_INDEX_WIDTH;
`else
// align to openpiton for the time being (this should be more configurable in the future)
// I$
localparam int unsigned ICACHE_INDEX_WIDTH = 12; // in bit
localparam int unsigned ICACHE_TAG_WIDTH = 44; // in bit
localparam int unsigned ICACHE_LINE_WIDTH = 128; // in bit
localparam int unsigned ICACHE_SET_ASSOC = 4;
// D$
localparam int unsigned DCACHE_INDEX_WIDTH = 12; // in bit
localparam int unsigned DCACHE_TAG_WIDTH = 44; // in bit
localparam int unsigned DCACHE_LINE_WIDTH = 128; // in bit
localparam int unsigned DCACHE_SET_ASSOC = 8;
// I$
localparam int unsigned ICACHE_INDEX_WIDTH = 12; // in bit
localparam int unsigned ICACHE_TAG_WIDTH = 44; // in bit
localparam int unsigned ICACHE_LINE_WIDTH = 128; // in bit
localparam int unsigned ICACHE_SET_ASSOC = 4;
// D$
localparam int unsigned DCACHE_INDEX_WIDTH = 12; // in bit
localparam int unsigned DCACHE_TAG_WIDTH = 44; // in bit
localparam int unsigned DCACHE_LINE_WIDTH = 128; // in bit
localparam int unsigned DCACHE_SET_ASSOC = 8;
`endif
// ---------------

2
openpiton/ariane_verilog_wrap.sv
View file

@ -14,7 +14,7 @@
// default to AXI64 cache ports if not using the
// serpent PULP extension
`ifndef SERPENT_PULP
`ifndef PITON_ARIANE
`ifndef AXI64_CACHE_PORTS
`define AXI64_CACHE_PORTS
`endif

10
src/ariane.sv
View file

@ -21,14 +21,14 @@ import instruction_tracer_pkg::*;
// default to AXI64 cache ports if not using the
// serpent PULP extension
`ifndef SERPENT_PULP
`ifndef PITON_ARIANE
`ifndef AXI64_CACHE_PORTS
`define AXI64_CACHE_PORTS
`endif
`endif
module ariane #(
`ifdef SERPENT_PULP
`ifdef PITON_ARIANE
parameter bit SwapEndianess = 0, // swap endianess in l15 adapter
parameter logic [63:0] CachedAddrEnd = 64'h80_0000_0000, // end of cached region
`endif
@ -578,7 +578,7 @@ module ariane #(
// Cache Subsystem
// -------------------
`ifdef SERPENT_PULP
`ifdef PITON_ARIANE
// this is a cache subsystem that is compatible with OpenPiton
serpent_cache_subsystem #(
.CachedAddrBeg ( CachedAddrBeg ),
@ -715,7 +715,7 @@ module ariane #(
end
endprogram
`ifdef SERPENT_PULP
`ifdef PITON_ARIANE
logic piton_pc_vld;
logic [63:0] piton_pc;
@ -746,7 +746,7 @@ module ariane #(
end
end
`endif // SERPENT_PULP
`endif // PITON_ARIANE
// mock tracer for Verilator, to be used with spike-dasm
`else

2
src/cache_subsystem/serpent_cache_subsystem.sv
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@ -18,7 +18,7 @@
// Description: Ariane cache subsystem that is compatible with the OpenPiton
// coherent memory system.
//
// Define SERPENT_PULP if you want to use this cache.
// Define PITON_ARIANE if you want to use this cache.
// Define AXI64_CACHE_PORTS if you want to use this cache
// with a standard 64bit AXI interace instead of the openpiton
// L1.5 interface.

2
tb/ariane_testharness.sv
View file

@ -539,7 +539,7 @@ module ariane_testharness #(
ariane_axi::resp_t axi_ariane_resp;
ariane #(
`ifdef SERPENT_PULP
`ifdef PITON_ARIANE
.SwapEndianess ( 0 ),
.CachedAddrEnd ( (ariane_soc::DRAMBase + ariane_soc::DRAMLength) ),
`endif