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🐛 Fix accidently taken misaligned exception

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This commit is contained in:
Florian Zaruba 2017-06-29 11:11:26 +02:00
parent cba2c9769d
commit 6a2aa65914
2 changed files with 4 additions and 4 deletions
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2
src/instr_realigner.sv
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@ -36,7 +36,7 @@ module instr_realigner (
// Registers
// ----------
// the last instruction was unaligned
logic unaligned_n, unaligned_q;
logic unaligned_n, unaligned_q;
// save the unaligned part of the instruction to this ff
logic [15:0] unaligned_instr_n, unaligned_instr_q;
// the previous instruction was compressed

6
src/lsu.sv
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@ -393,8 +393,8 @@ module lsu #(
data_misaligned = 1'b0;
if(lsu_valid_i) begin
case (operator_i)
if(lsu_ctrl.valid) begin
case (lsu_ctrl.operator)
// double word
LD, SD: begin
if (lsu_ctrl.vaddr[2:0] != 3'b000)
@ -408,7 +408,7 @@ module lsu #(
// half word
LH, LHU, SH: begin
if (vaddr_i[0] != 1'b0)
if (lsu_ctrl.vaddr[0] != 1'b0)
data_misaligned = 1'b1;
end
// byte -> is always aligned