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docs: more fixes (#2412)
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2249202769
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3 changed files with 249 additions and 103 deletions
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@ -552,7 +552,7 @@ class AdocAddressBlock(AddressBlockClass):
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return "RO"
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else:
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return "RW"
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def generate_label(self, name):
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return "_" + name.replace('[','').replace(']','').upper()
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@ -573,24 +573,24 @@ class AdocAddressBlock(AddressBlockClass):
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r += " SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1\n"
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r += " Author: Abdessamii Oukalrazqou\n"
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r += "////\n\n"
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r += "=== %s\n\n"%self.name
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r += "==== Conventions\n\n"
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r += "In the subsequent sections, register fields are labeled with one of the following abbreviations:\n\n"
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r += "* WPRI (Writes Preserve Values, Reads Ignore Values): read/write field reserved\n"
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r += "for future use. For forward compatibility, implementations that do not\n"
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r += "furnish these fields must make them read-only zero.\n"
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r += "* WLRL (Write/Read Only Legal Values): read/write CSR field that specifies\n"
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r += "behavior for only a subset of possible bit encodings, with other bit encodings\n"
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r += "reserved.\n"
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r += "* WARL (Write Any Values, Reads Legal Values): read/write CSR fields which are\n"
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r += "only defined for a subset of bit encodings, but allow any value to be written\n"
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r += "while guaranteeing to return a legal value whenever read.\n"
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r += "* ROCST (Read-Only Constant): A special case of WARL field which admits only one\n"
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r += "legal value, and therefore, behaves as a constant field that silently ignores\n"
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r += "writes.\n"
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@ -598,12 +598,12 @@ class AdocAddressBlock(AddressBlockClass):
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r += "* ROVAR (Read-Only Variable): A special case of WARL field which can take\n"
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r += "multiple legal values but cannot be modified by software and depends only on\n"
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r += "the architectural state of the hart.\n\n"
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r += "In particular, a register that is not internally divided\n"
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r += "into multiple fields can be considered as containing a single field of XLEN bits.\n"
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r += "This allows to clearly represent read-write registers holding a single legal value\n"
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r += "(typically zero).\n\n"
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r += "==== Register Summary\n\n"
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r += "|===\n"
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@ -629,7 +629,7 @@ class AdocAddressBlock(AddressBlockClass):
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# RO/RW privileges are encoded in register address.
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r += "Privilege:: %s\n"%(reg.access + self.get_access_privilege(reg))
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r += "Description:: %s\n\n"%(reg.desc)
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reg_table = []
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for field in reg.field:
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if field.bitWidth == 1: # only one bit -> no range needed
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@ -658,10 +658,12 @@ class AdocAddressBlock(AddressBlockClass):
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r += "| Bits | Field Name | Reset Value | Type | Legal Values | Description\n\n"
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for reg in reg_table:
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for col in reg:
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r +="| %s "%col.replace('\n','')
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if col == 'Reserved':
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col = "_Reserved_"
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r +="| %s "%col.replace('\n','').replace('|', '\|')
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r += "\n"
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r += "|===\n\n"
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return r
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class InstadocBlock(InstructionBlockClass):
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@ -678,7 +680,7 @@ class InstadocBlock(InstructionBlockClass):
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InstrNameList = [reg.key for reg in self.Instructionlist]
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InstrDescrList = [reg.descr for reg in self.Instructionlist]
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InstrExtList = [reg.Extension_Name for reg in self.Instructionlist]
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r += "////\n"
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r += " Copyright (c) 2024 OpenHW Group\n"
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r += " Copyright (c) 2024 Thales\n"
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@ -688,7 +690,7 @@ class InstadocBlock(InstructionBlockClass):
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r += "=== %s\n\n"%self.name
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r += "==== Instructions\n\n"
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r += "|===\n"
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r += "|Subset Name | Name | Description\n\n"
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for i, _ in enumerate(InstrNameList):
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@ -696,7 +698,7 @@ class InstadocBlock(InstructionBlockClass):
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str(InstrNameList[i]),
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str(InstrDescrList[i]).replace('\n',''))
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r += "|===\n\n"
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for reg in self.Instructionlist:
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reg_table = []
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if len(reg.Name) > 0:
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@ -1106,7 +1108,7 @@ class CsrParser:
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legal = ""
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fieldaccess = "WPRI"
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bitWidth = int(item_[len(item_) - 1]) - int(item_[0]) + 1
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fieldDesc = "*Reserved*"
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fieldDesc = "Reserved"
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bitlegal = legal
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fieldreset = hex(
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int(resetValue, 16) >> (bitlsb) & ((1 << ((bitWidth))) - 1)
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