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add CVA6ConfigFpgaAltera parameter (#2590)

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First step to add FpgaAltera optimization parameter
This commit is contained in:
AngelaGonzalezMarino 2024-11-12 20:27:15 +01:00 • committed by GitHub
parent 16f37b95e6
commit 6a86ebd2af
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GPG key ID: B5690EEEBB952194
18 changed files with 37 additions and 45 deletions
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5
core/include/build_config_pkg.sv
View file

@ -42,6 +42,7 @@ package build_config_pkg;
cfg.VMID_WIDTH = (CVA6Cfg.XLEN == 64) ? 14 : 1;
cfg.FpgaEn = CVA6Cfg.FpgaEn;
cfg.FpgaAlteraEn = CVA6Cfg.FpgaAlteraEn;
cfg.TechnoCut = CVA6Cfg.TechnoCut;
cfg.SuperscalarEn = CVA6Cfg.SuperscalarEn;
@ -122,7 +123,7 @@ package build_config_pkg;
cfg.AxiBurstWriteEn = CVA6Cfg.AxiBurstWriteEn;
cfg.ICACHE_SET_ASSOC = CVA6Cfg.IcacheSetAssoc;
cfg.ICACHE_SET_ASSOC_WIDTH = $clog2(CVA6Cfg.IcacheSetAssoc);
cfg.ICACHE_SET_ASSOC_WIDTH = CVA6Cfg.IcacheSetAssoc > 1 ? $clog2(CVA6Cfg.IcacheSetAssoc) : CVA6Cfg.IcacheSetAssoc;
cfg.ICACHE_INDEX_WIDTH = ICACHE_INDEX_WIDTH;
cfg.ICACHE_TAG_WIDTH = cfg.PLEN - ICACHE_INDEX_WIDTH;
cfg.ICACHE_LINE_WIDTH = CVA6Cfg.IcacheLineWidth;
@ -130,7 +131,7 @@ package build_config_pkg;
cfg.DCacheType = CVA6Cfg.DCacheType;
cfg.DcacheIdWidth = CVA6Cfg.DcacheIdWidth;
cfg.DCACHE_SET_ASSOC = CVA6Cfg.DcacheSetAssoc;
cfg.DCACHE_SET_ASSOC_WIDTH = $clog2(CVA6Cfg.DcacheSetAssoc);
cfg.DCACHE_SET_ASSOC_WIDTH = CVA6Cfg.DcacheSetAssoc > 1 ? $clog2(CVA6Cfg.DcacheSetAssoc) : CVA6Cfg.DcacheSetAssoc;
cfg.DCACHE_INDEX_WIDTH = DCACHE_INDEX_WIDTH;
cfg.DCACHE_TAG_WIDTH = cfg.PLEN - DCACHE_INDEX_WIDTH;
cfg.DCACHE_LINE_WIDTH = CVA6Cfg.DcacheLineWidth;

5
core/include/config_pkg.sv
View file

@ -168,8 +168,10 @@ package config_pkg;
int unsigned FetchUserEn;
// Width of fetch user field
int unsigned FetchUserWidth;
// Is FPGA optimization of CV32A6
// Is FPGA optimization of CV32A6 for Xilinx and Altera
bit FpgaEn;
// Is FPGA optimization for Altera FPGA
bit FpgaAlteraEn;
// Is Techno Cut instanciated
bit TechnoCut;
// Enable superscalar* with 2 issue ports and 2 commit ports.
@ -214,6 +216,7 @@ package config_pkg;
int unsigned VMID_WIDTH;
bit FpgaEn;
bit FpgaAlteraEn;
bit TechnoCut;
bit SuperscalarEn;

5
core/include/cv32a60x_config_pkg_deprecated.sv
View file

@ -52,8 +52,6 @@ package cva6_config_pkg;
localparam CVA6ConfigNrCommitPorts = 1;
localparam CVA6ConfigNrScoreboardEntries = 4;
localparam CVA6ConfigFpgaEn = 0;
localparam CVA6ConfigNrLoadPipeRegs = 1;
localparam CVA6ConfigNrStorePipeRegs = 0;
localparam CVA6ConfigNrLoadBufEntries = 2;
@ -76,7 +74,8 @@ package cva6_config_pkg;
localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
XLEN: unsigned'(CVA6ConfigXlen),
FpgaEn: bit'(CVA6ConfigFpgaEn),
FpgaEn: bit'(0), // for Xilinx and Altera
FpgaAlteraEn: bit'(0), // for Altera (only)
TechnoCut: bit'(0),
NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts),
AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),

1
core/include/cv32a65x_config_pkg.sv
View file

@ -22,6 +22,7 @@ package cva6_config_pkg;
XLEN: unsigned'(CVA6ConfigXlen),
VLEN: unsigned'(32),
FpgaEn: bit'(0),
FpgaAlteraEn: bit'(0),
TechnoCut: bit'(1),
SuperscalarEn: bit'(1),
NrCommitPorts: unsigned'(1),

5
core/include/cv32a6_embedded_config_pkg_deprecated.sv
View file

@ -51,8 +51,6 @@ package cva6_config_pkg;
localparam CVA6ConfigNrCommitPorts = 1;
localparam CVA6ConfigNrScoreboardEntries = 4;
localparam CVA6ConfigFpgaEn = 0;
localparam CVA6ConfigNrLoadPipeRegs = 0;
localparam CVA6ConfigNrStorePipeRegs = 0;
localparam CVA6ConfigNrLoadBufEntries = 1;
@ -75,7 +73,8 @@ package cva6_config_pkg;
localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
XLEN: unsigned'(CVA6ConfigXlen),
FpgaEn: bit'(CVA6ConfigFpgaEn),
FpgaEn: bit'(0), // for Xilinx and Altera
FpgaAlteraEn: bit'(0), // for Altera (only)
TechnoCut: bit'(0),
NrCommitPorts: unsigned'(CVA6ConfigNrCommitPorts),
AxiAddrWidth: unsigned'(CVA6ConfigAxiAddrWidth),

5
core/include/cv32a6_ima_sv32_fpga_config_pkg.sv
View file

@ -50,8 +50,6 @@ package cva6_config_pkg;
localparam CVA6ConfigNrScoreboardEntries = 4;
localparam CVA6ConfigFpgaEn = 1;
localparam CVA6ConfigNrLoadPipeRegs = 1;
localparam CVA6ConfigNrStorePipeRegs = 0;
localparam CVA6ConfigNrLoadBufEntries = 2;
@ -75,7 +73,8 @@ package cva6_config_pkg;
localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
XLEN: unsigned'(CVA6ConfigXlen),
VLEN: unsigned'(32),
FpgaEn: bit'(CVA6ConfigFpgaEn),
FpgaEn: bit'(1), // for Xilinx and Altera
FpgaAlteraEn: bit'(0), // for Altera (only)
TechnoCut: bit'(0),
SuperscalarEn: bit'(0),
NrCommitPorts: unsigned'(1),

5
core/include/cv32a6_imac_sv0_config_pkg.sv
View file

@ -51,8 +51,6 @@ package cva6_config_pkg;
localparam CVA6ConfigNrScoreboardEntries = 8;
localparam CVA6ConfigNrLoadBufEntries = 2;
localparam CVA6ConfigFpgaEn = 0;
localparam CVA6ConfigNrLoadPipeRegs = 1;
localparam CVA6ConfigNrStorePipeRegs = 0;
@ -75,7 +73,8 @@ package cva6_config_pkg;
localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
XLEN: unsigned'(CVA6ConfigXlen),
VLEN: unsigned'(32),
FpgaEn: bit'(CVA6ConfigFpgaEn),
FpgaEn: bit'(0), // for Xilinx and Altera
FpgaAlteraEn: bit'(0), // for Altera (only)
TechnoCut: bit'(0),
SuperscalarEn: bit'(0),
NrCommitPorts: unsigned'(2),

5
core/include/cv32a6_imac_sv32_config_pkg.sv
View file

@ -50,8 +50,6 @@ package cva6_config_pkg;
localparam CVA6ConfigNrScoreboardEntries = 8;
localparam CVA6ConfigFpgaEn = 0;
localparam CVA6ConfigNrLoadPipeRegs = 1;
localparam CVA6ConfigNrStorePipeRegs = 0;
localparam CVA6ConfigNrLoadBufEntries = 2;
@ -75,7 +73,8 @@ package cva6_config_pkg;
localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
XLEN: unsigned'(CVA6ConfigXlen),
VLEN: unsigned'(32),
FpgaEn: bit'(CVA6ConfigFpgaEn),
FpgaEn: bit'(0), // for Xilinx and Altera
FpgaAlteraEn: bit'(0), // for Altera (only)
TechnoCut: bit'(0),
SuperscalarEn: bit'(0),
NrCommitPorts: unsigned'(2),

5
core/include/cv32a6_imafc_sv32_config_pkg.sv
View file

@ -50,8 +50,6 @@ package cva6_config_pkg;
localparam CVA6ConfigNrScoreboardEntries = 8;
localparam CVA6ConfigFpgaEn = 0;
localparam CVA6ConfigNrLoadPipeRegs = 1;
localparam CVA6ConfigNrStorePipeRegs = 0;
localparam CVA6ConfigNrLoadBufEntries = 2;
@ -75,7 +73,8 @@ package cva6_config_pkg;
localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
XLEN: unsigned'(CVA6ConfigXlen),
VLEN: unsigned'(32),
FpgaEn: bit'(CVA6ConfigFpgaEn),
FpgaEn: bit'(0), // for Xilinx and Altera
FpgaAlteraEn: bit'(0), // for Altera (only)
TechnoCut: bit'(0),
SuperscalarEn: bit'(0),
NrCommitPorts: unsigned'(2),

5
core/include/cv64a6_imadfcv_sv39_polara_config_pkg.sv
View file

@ -50,8 +50,6 @@ package cva6_config_pkg;
localparam CVA6ConfigNrScoreboardEntries = 8;
localparam CVA6ConfigFpgaEn = 0;
localparam CVA6ConfigNrLoadPipeRegs = 1;
localparam CVA6ConfigNrStorePipeRegs = 0;
localparam CVA6ConfigNrLoadBufEntries = 2;
@ -75,7 +73,8 @@ package cva6_config_pkg;
localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
XLEN: unsigned'(CVA6ConfigXlen),
VLEN: unsigned'(64),
FpgaEn: bit'(CVA6ConfigFpgaEn),
FpgaEn: bit'(0), // for Xilinx and Altera
FpgaAlteraEn: bit'(0), // for Altera (only)
TechnoCut: bit'(0),
SuperscalarEn: bit'(0),
NrCommitPorts: unsigned'(2),

5
core/include/cv64a6_imafdc_sv39_config_pkg.sv
View file

@ -50,8 +50,6 @@ package cva6_config_pkg;
localparam CVA6ConfigNrScoreboardEntries = 8;
localparam CVA6ConfigFpgaEn = 0;
localparam CVA6ConfigNrLoadPipeRegs = 1;
localparam CVA6ConfigNrStorePipeRegs = 0;
localparam CVA6ConfigNrLoadBufEntries = 2;
@ -75,7 +73,8 @@ package cva6_config_pkg;
localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
XLEN: unsigned'(CVA6ConfigXlen),
VLEN: unsigned'(64),
FpgaEn: bit'(CVA6ConfigFpgaEn),
FpgaEn: bit'(0), // for Xilinx and Altera
FpgaAlteraEn: bit'(0), // for Altera (only)
TechnoCut: bit'(0),
SuperscalarEn: bit'(0),
NrCommitPorts: unsigned'(2),

5
core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv
View file

@ -57,8 +57,6 @@ package cva6_config_pkg;
localparam CVA6ConfigNrScoreboardEntries = 8;
localparam CVA6ConfigFpgaEn = 0;
localparam CVA6ConfigNrLoadPipeRegs = 1;
localparam CVA6ConfigNrStorePipeRegs = 0;
localparam CVA6ConfigNrLoadBufEntries = 8;
@ -82,7 +80,8 @@ package cva6_config_pkg;
localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
XLEN: unsigned'(CVA6ConfigXlen),
VLEN: unsigned'(64),
FpgaEn: bit'(CVA6ConfigFpgaEn),
FpgaEn: bit'(0), // for Xilinx and Altera
FpgaAlteraEn: bit'(0), // for Altera (only)
TechnoCut: bit'(0),
SuperscalarEn: bit'(0),
NrCommitPorts: unsigned'(2),

5
core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv
View file

@ -50,8 +50,6 @@ package cva6_config_pkg;
localparam CVA6ConfigNrScoreboardEntries = 8;
localparam CVA6ConfigFpgaEn = 0;
localparam CVA6ConfigNrLoadPipeRegs = 1;
localparam CVA6ConfigNrStorePipeRegs = 0;
localparam CVA6ConfigNrLoadBufEntries = 2;
@ -75,7 +73,8 @@ package cva6_config_pkg;
localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
XLEN: unsigned'(CVA6ConfigXlen),
VLEN: unsigned'(64),
FpgaEn: bit'(CVA6ConfigFpgaEn),
FpgaEn: bit'(0), // for Xilinx and Altera
FpgaAlteraEn: bit'(0), // for Altera (only)
TechnoCut: bit'(0),
SuperscalarEn: bit'(0),
NrCommitPorts: unsigned'(2),

5
core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv
View file

@ -50,8 +50,6 @@ package cva6_config_pkg;
localparam CVA6ConfigNrScoreboardEntries = 8;
localparam CVA6ConfigFpgaEn = 0;
localparam CVA6ConfigNrLoadPipeRegs = 1;
localparam CVA6ConfigNrStorePipeRegs = 0;
localparam CVA6ConfigNrLoadBufEntries = 2;
@ -75,7 +73,8 @@ package cva6_config_pkg;
localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
XLEN: unsigned'(CVA6ConfigXlen),
VLEN: unsigned'(64),
FpgaEn: bit'(CVA6ConfigFpgaEn),
FpgaEn: bit'(0), // for Xilinx and Altera
FpgaAlteraEn: bit'(0), // for Altera (only)
TechnoCut: bit'(0),
SuperscalarEn: bit'(0),
NrCommitPorts: unsigned'(2),

5
core/include/cv64a6_imafdch_sv39_config_pkg.sv
View file

@ -50,8 +50,6 @@ package cva6_config_pkg;
localparam CVA6ConfigNrScoreboardEntries = 8;
localparam CVA6ConfigFpgaEn = 0;
localparam CVA6ConfigNrLoadPipeRegs = 1;
localparam CVA6ConfigNrStorePipeRegs = 0;
localparam CVA6ConfigNrLoadBufEntries = 2;
@ -75,7 +73,8 @@ package cva6_config_pkg;
localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
XLEN: unsigned'(CVA6ConfigXlen),
VLEN: unsigned'(64),
FpgaEn: bit'(CVA6ConfigFpgaEn),
FpgaEn: bit'(0), // for Xilinx and Altera
FpgaAlteraEn: bit'(0), // for Altera (only)
TechnoCut: bit'(0),
SuperscalarEn: bit'(0),
NrCommitPorts: unsigned'(2),

5
core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv
View file

@ -50,8 +50,6 @@ package cva6_config_pkg;
localparam CVA6ConfigNrScoreboardEntries = 8;
localparam CVA6ConfigFpgaEn = 0;
localparam CVA6ConfigNrLoadPipeRegs = 1;
localparam CVA6ConfigNrStorePipeRegs = 0;
localparam CVA6ConfigNrLoadBufEntries = 2;
@ -75,7 +73,8 @@ package cva6_config_pkg;
localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
XLEN: unsigned'(CVA6ConfigXlen),
VLEN: unsigned'(64),
FpgaEn: bit'(CVA6ConfigFpgaEn),
FpgaEn: bit'(0), // for Xilinx and Altera
FpgaAlteraEn: bit'(0), // for Altera (only)
TechnoCut: bit'(0),
SuperscalarEn: bit'(0),
NrCommitPorts: unsigned'(2),

5
core/include/cv64a6_imafdcv_sv39_config_pkg.sv
View file

@ -50,8 +50,6 @@ package cva6_config_pkg;
localparam CVA6ConfigNrScoreboardEntries = 8;
localparam CVA6ConfigFpgaEn = 0;
localparam CVA6ConfigNrLoadPipeRegs = 1;
localparam CVA6ConfigNrStorePipeRegs = 0;
localparam CVA6ConfigNrLoadBufEntries = 2;
@ -75,7 +73,8 @@ package cva6_config_pkg;
localparam config_pkg::cva6_user_cfg_t cva6_cfg = '{
XLEN: unsigned'(CVA6ConfigXlen),
VLEN: unsigned'(64),
FpgaEn: bit'(CVA6ConfigFpgaEn),
FpgaEn: bit'(0), // for Xilinx and Altera
FpgaAlteraEn: bit'(0), // for Altera (only)
TechnoCut: bit'(0),
SuperscalarEn: bit'(0),
NrCommitPorts: unsigned'(1),

1
core/include/cv64a6_mmu_config_pkg.sv
View file

@ -29,6 +29,7 @@ package cva6_config_pkg;
XLEN: unsigned'(CVA6ConfigXlen),
VLEN: unsigned'(64),
FpgaEn: bit'(0),
FpgaAlteraEn: bit'(0),
TechnoCut: bit'(0),
SuperscalarEn: bit'(0),
NrCommitPorts: unsigned'(1),