Minor syntax fixes, DPI build clean-up

Makefile

@@ -34,7 +34,8 @@ sequences := $(wildcard tb/sequences/*/*.sv*)
 # Test packages
 test_pkg := $(wildcard tb/test/*/*sequence_pkg.sv*) $(wildcard tb/test/*/*_pkg.sv*)
 # DPI
-dpi := $(wildcard tb/dpi/*)
+dpi := $(patsubst tb/dpi/%.cc,work/%.o,$(wildcard tb/dpi/*.cc))
+dpi_hdr := $(wildcard tb/dpi/*.h)
 # this list contains the standalone components
 src := $(wildcard src/*.sv) $(wildcard tb/common/*.sv) $(wildcard tb/common/*.v) $(wildcard src/axi2per/*.sv)  \
        $(wildcard src/axi_slice/*.sv)                                                                          \
@@ -63,7 +64,7 @@ list_incdir := $(foreach dir, ${incdir}, +incdir+$(dir))
 
 # Build the TB and module using QuestaSim
 build: $(library) $(library)/.build-agents $(library)/.build-interfaces $(library)/.build-components \
-		$(library)/.build-srcs $(library)/.build-tb $(library)/.build-dpi
+		$(library)/.build-srcs $(library)/.build-tb $(library)/ariane_dpi.so
 		# Optimize top level
 	vopt$(questa_version) $(compile_flag) -work $(library)  $(test_top_level) -o $(test_top_level)_optimized +acc -check_synthesis
 
@@ -82,12 +83,12 @@ $(library)/.build-tb: $(dpi) $(tbs)
 	touch $(library)/.build-tb
 
 # compile DPIs
-$(library)/.build-dpi: $(dpi)
+work/%.o: tb/dpi/%.cc $(dpi_hdr)
+	$(CXX) -shared -fPIC -std=c++0x -Bsymbolic -I$(QUESTASIM_HOME)/include -o $@ $<
+
+$(library)/ariane_dpi.so: $(dpi)
 	# Compile C-code and generate .so file
-	# g++ -lfesvr -c -fPIC -m64 -std=c++0x -I$(QUESTASIM_HOME)/include -o $(library)/ariane_dpi.o tb/dpi/SimDTM.cc
-	# g++ -shared -m64 -o $(library)/ariane_dpi.so $(library)/ariane_dpi.o -lfesvr
-	gcc -shared -fPIC -std=c++0x -Bsymbolic -I$(QUESTASIM_HOME)/include -o work/ariane_dpi.so tb/dpi/SimDTM.cc -lfesvr -lstdc++
-	touch $(library)/.build-dpi
+	g++ -shared -m64 -o $(library)/ariane_dpi.so $? -lfesvr
 
 # Compile Sequences and Tests
 $(library)/.build-components: $(envs) $(sequences) $(test_pkg)
@@ -109,12 +110,12 @@ $(library):
 	# Create the library
 	vlib${questa_version} ${library}
 
-sim: build
+sim: build $(library)/ariane_dpi.so
 	vsim${questa_version} +permissive -64 -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
 	 +BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=HIGH" -coverage -classdebug\
 	 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi -do "run -all; do tb/wave/wave_core.do; exit" ${top_level}_optimized +permissive-off ++$(riscv-test)
 
-simc: build
+simc: build $(library)/ariane_dpi.so
 	vsim${questa_version} +permissive -64 -c -lib ${library} +max-cycles=$(max_cycles) +UVM_TESTNAME=${test_case} \
 	 +BASEDIR=$(riscv-test-dir) $(uvm-flags) "+UVM_VERBOSITY=HIGH" -coverage -classdebug\
 	 -gblso $(RISCV)/lib/libfesvr.so -sv_lib $(library)/ariane_dpi -do "run -all; do tb/wave/wave_core.do; exit" ${top_level}_optimized +permissive-off ++$(riscv-test)

src/debug/dmi_cdc.sv

@@ -23,10 +23,10 @@ module dmi_cdc (
 
     input  logic                    mem_valid_i,
     output logic                    mem_gnt_o,
-    input  logic [AddrWidth-1:0]    mem_addr_i,
+    input  logic [6:0]              mem_addr_i,
     input  logic                    mem_we_i,
-    input  logic [DataWidth-1:0]    mem_wdata_i,
-    output logic [DataWidth-1:0]    mem_rdata_o,
+    input  logic [31:0]             mem_wdata_i,
+    output logic [31:0]             mem_rdata_o,
     output logic                    mem_rvalid_o,
 
     // Memory -> Slave side

src/debug/dmi_jtag.sv

@@ -99,7 +99,7 @@ module dmi_jtag (
         case (state_q)
             Idle: begin
                 // make sure that no error is sticky
-                if (dmi_access && update_dr && (error_q == 0)) begin
+                if (dmi_access && update_dr && (error_q == DMINoError)) begin
                     // save address and value
                     address_d = dmi.address;
                     data_d = dmi.data;
@@ -173,7 +173,7 @@ module dmi_jtag (
             state_q   <= Idle;
             address_q <= '0;
             data_q    <= '0;
-            error_q   <= '0;
+            error_q   <= DMINoError;
         end else begin
             dr_q      <= dr_d;
             state_q   <= state_d;

src/debug/dmi_jtag_tap.sv

@@ -41,7 +41,7 @@ module dmi_jtag_tap #(
     // test data to submodule
     output logic        dmi_tdi_o,
     // test data in from submodule
-    output logic        dmi_tdo_i
+    input  logic        dmi_tdo_i
 
 );
 
@@ -80,7 +80,6 @@ module dmi_jtag_tap #(
     always_comb begin
         jtag_ir_shift_d = jtag_ir_shift_q;
         jtag_ir_d       = jtag_ir_q;
-        bypass_d        = bypass_q;
 
         // IR shift register
         if (shift_ir) begin

tb

@@ -1 +1 @@
-Subproject commit d8f7666f1bb520d9edcced48ca1737614dc63b51
+Subproject commit e0187d11b81c1c27a20b4f514a4be2b2bd75ced7