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https://github.com/openhwgroup/cva6.git
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VM based RISC-V tests are passing
This commit is contained in:
Florian Zaruba
parent
f2d45c007b
commit
6c66ea19ae
5 changed files with 102 additions and 83 deletions
24
Makefile
24
Makefile
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@ -54,18 +54,18 @@ riscv-tests := rv64ui-p-add rv64ui-p-addi rv64ui-p-slli rv64ui-p-addiw rv64ui-p-
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rv64ui-p-lb rv64ui-p-lbu rv64ui-p-ld rv64ui-p-lh rv64ui-p-lhu rv64ui-p-lui rv64ui-p-lw rv64ui-p-lwu \
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rv64mi-p-csr rv64mi-p-mcsr rv64mi-p-illegal rv64mi-p-ma_addr rv64mi-p-ma_fetch rv64mi-p-sbreak rv64mi-p-scall \
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rv64si-p-csr rv64si-p-ma_fetch rv64si-p-scall rv64si-p-wfi rv64si-p-sbreak rv64si-p-dirty \
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rv64uc-p-rvc
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# rv64ui-v-add rv64ui-v-addi rv64ui-p-slli rv64ui-v-addiw rv64ui-v-addw rv64ui-v-and rv64ui-v-auipc \
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# rv64ui-v-beq rv64ui-v-bge rv64ui-v-bgeu rv64ui-v-andi rv64ui-v-blt rv64ui-v-bltu rv64ui-v-bne \
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# rv64ui-v-simple rv64ui-v-jal rv64ui-v-jalr rv64ui-v-or rv64ui-v-ori rv64ui-v-sub rv64ui-v-subw \
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# rv64ui-v-xor rv64ui-v-xori rv64ui-v-slliw rv64ui-v-sll rv64ui-v-slli rv64ui-v-slliw \
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# rv64ui-v-slt rv64ui-v-slti rv64ui-v-sltiu rv64ui-v-sltu rv64ui-v-sra rv64ui-v-srai \
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# rv64ui-v-sraiw rv64ui-v-sraw rv64ui-v-srl rv64ui-v-srli rv64ui-v-srliw rv64ui-v-srlw \
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# rv64ui-v-lb rv64ui-v-lbu rv64ui-v-ld rv64ui-v-lh rv64ui-v-lhu rv64ui-v-lui \
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# rv64um-p-mul rv64um-p-mulh rv64um-p-mulhsu rv64um-p-mulhu rv64um-p-div rv64um-p-divu rv64um-p-rem \
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# rv64um-p-remu rv64um-p-mulw rv64um-p-divw rv64um-p-divuw rv64um-p-remw rv64um-p-remuw \
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# rv64um-v-mul rv64um-v-mulh rv64um-v-mulhsu rv64um-v-mulhu rv64um-v-div rv64um-v-divu rv64um-v-rem \
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# rv64um-v-remu rv64um-v-mulw rv64um-v-divw rv64um-v-divuw rv64um-v-remw rv64um-v-remuw
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rv64uc-p-rvc \
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rv64ui-v-add rv64ui-v-addi rv64ui-p-slli rv64ui-v-addiw rv64ui-v-addw rv64ui-v-and rv64ui-v-auipc \
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rv64ui-v-beq rv64ui-v-bge rv64ui-v-bgeu rv64ui-v-andi rv64ui-v-blt rv64ui-v-bltu rv64ui-v-bne \
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rv64ui-v-simple rv64ui-v-jal rv64ui-v-jalr rv64ui-v-or rv64ui-v-ori rv64ui-v-sub rv64ui-v-subw \
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rv64ui-v-xor rv64ui-v-xori rv64ui-v-slliw rv64ui-v-sll rv64ui-v-slli rv64ui-v-slliw \
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rv64ui-v-slt rv64ui-v-slti rv64ui-v-sltiu rv64ui-v-sltu rv64ui-v-sra rv64ui-v-srai \
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rv64ui-v-sraiw rv64ui-v-sraw rv64ui-v-srl rv64ui-v-srli rv64ui-v-srliw rv64ui-v-srlw \
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rv64ui-v-lb rv64ui-v-lbu rv64ui-v-ld rv64ui-v-lh rv64ui-v-lhu rv64ui-v-lui \
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rv64um-p-mul rv64um-p-mulh rv64um-p-mulhsu rv64um-p-mulhu rv64um-p-div rv64um-p-divu rv64um-p-rem \
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rv64um-p-remu rv64um-p-mulw rv64um-p-divw rv64um-p-divuw rv64um-p-remw rv64um-p-remuw \
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rv64um-v-mul rv64um-v-mulh rv64um-v-mulhsu rv64um-v-mulhu rv64um-v-div rv64um-v-divu rv64um-v-rem \
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rv64um-v-remu rv64um-v-mulw rv64um-v-divw rv64um-v-divuw rv64um-v-remw rv64um-v-remuw
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# failed test directory
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failed-tests := $(wildcard failedtests/*.S)
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@ -286,8 +286,6 @@ module ariane #(
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.*
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);
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assign fetch_req_if_ex = 1'b0;
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// ---------
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// ID
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// ---------
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@ -65,6 +65,8 @@ module frontend #(
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// Registers
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logic [31:0] icache_data_d, icache_data_q;
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logic icache_valid_d, icache_valid_q;
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exception_t icache_ex_d, icache_ex_q;
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logic instruction_valid;
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logic icache_speculative_d, icache_speculative_q;
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@ -384,6 +386,7 @@ module frontend #(
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icache_valid_q <= 1'b0;
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icache_speculative_q <= 1'b0;
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icache_vaddr_q <= 'b0;
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icache_ex_q <= '0;
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unaligned_q <= 1'b0;
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unaligned_address_q <= '0;
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unaligned_instr_q <= '0;
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@ -393,6 +396,7 @@ module frontend #(
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icache_valid_q <= icache_valid_d;
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icache_speculative_q <= icache_speculative_d;
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icache_vaddr_q <= icache_vaddr_d;
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icache_ex_q <= icache_ex_d;
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unaligned_q <= unaligned_d;
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unaligned_address_q <= unaligned_address_d;
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unaligned_instr_q <= unaligned_instr_d;
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@ -434,21 +438,21 @@ module frontend #(
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.CACHE_LINE_WIDTH ( 128 ),
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.FETCH_WIDTH ( FETCH_WIDTH )
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) i_icache (
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.clk_i ( clk_i ),
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.rst_ni ( rst_ni ),
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.flush_i ( flush_icache_i ),
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.vaddr_i ( fetch_vaddr ), // 1st cycle
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.is_speculative_i ( fetch_is_speculative ), // 1st cycle
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.data_o ( icache_data_d ),
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.req_i ( icache_req ),
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.kill_s1_i ( kill_s1 ),
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.kill_s2_i ( kill_s2 ),
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.kill_s1_i ( kill_s1 ),
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.kill_s2_i ( kill_s2 ),
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.ready_o ( icache_ready ),
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.valid_o ( icache_valid_d ),
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.ex_o ( icache_ex_d ),
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.is_speculative_o ( icache_speculative_d ),
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.vaddr_o ( icache_vaddr_d ),
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.axi ( axi ),
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.miss_o ( l1_icache_miss_o )
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.miss_o ( l1_icache_miss_o ),
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.*
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);
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for (genvar i = 0; i < INSTR_PER_FETCH; i++) begin
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@ -471,13 +475,10 @@ module frontend #(
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);
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end
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exception_t ex;
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assign ex = '0;
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fetch_fifo i_fetch_fifo (
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.flush_i ( flush_i ),
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.branch_predict_i ( bp_sbe ),
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.ex_i ( ex ),
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.ex_i ( icache_ex_q ),
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.addr_i ( icache_vaddr_q ),
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.rdata_i ( icache_data_q ),
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.valid_i ( fifo_valid ),
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@ -670,8 +671,8 @@ module bht #(
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logic [1:0] saturation_counter;
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} bht_d[NR_ENTRIES-1:0], bht_q[NR_ENTRIES-1:0];
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logic [$clog2(NR_ENTRIES)-1:0] index, update_pc;
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logic [1:0] saturation_counter;
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logic [$clog2(NR_ENTRIES)-1:0] index, update_pc;
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logic [1:0] saturation_counter;
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assign index = vpc_i[PREDICTION_BITS - 1:OFFSET];
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assign update_pc = bht_update_i.pc[PREDICTION_BITS - 1:OFFSET];
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134
src/icache.sv
134
src/icache.sv
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@ -13,36 +13,46 @@
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// ------------------------------
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// Instruction Cache
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// ------------------------------
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import ariane_pkg::*;
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module icache #(
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parameter int unsigned SET_ASSOCIATIVITY = 4,
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parameter int unsigned INDEX_WIDTH = 12, // in bit
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parameter int unsigned TAG_WIDTH = 44, // in bit
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parameter int unsigned CACHE_LINE_WIDTH = 64, // in bit
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parameter int unsigned FETCH_WIDTH = 32 // in bit
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)(
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input logic clk_i,
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input logic rst_ni,
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input logic flush_i, // flush the icache, flush and kill have to be asserted together
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input logic req_i, // we request a new word
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input logic is_speculative_i, // is this request speculative or not
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input logic kill_s1_i, // kill the current request
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input logic kill_s2_i, // kill the last request
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output logic ready_o, // icache is ready
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input logic [63:0] vaddr_i, // 1st cycle: 12 bit index is taken for lookup
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output logic [FETCH_WIDTH-1:0] data_o, // 2+ cycle out: tag
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output logic is_speculative_o, // the fetch was speculative
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output logic [63:0] vaddr_o, // virtual address out
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output logic valid_o, // signals a valid read
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output logic miss_o, // we missed on the cache
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AXI_BUS.Master axi
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);
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parameter int unsigned SET_ASSOCIATIVITY = 4,
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parameter int unsigned INDEX_WIDTH = 12, // in bit
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parameter int unsigned TAG_WIDTH = 44, // in bit
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parameter int unsigned CACHE_LINE_WIDTH = 64, // in bit
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parameter int unsigned FETCH_WIDTH = 32 // in bit
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)(
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input logic clk_i,
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input logic rst_ni,
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input logic flush_i, // flush the icache, flush and kill have to be asserted together
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input logic req_i, // we request a new word
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input logic is_speculative_i, // is this request speculative or not
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input logic kill_s1_i, // kill the current request
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input logic kill_s2_i, // kill the last request
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output logic ready_o, // icache is ready
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input logic [63:0] vaddr_i, // 1st cycle: 12 bit index is taken for lookup
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output logic [FETCH_WIDTH-1:0] data_o, // 2+ cycle out: tag
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output logic is_speculative_o, // the fetch was speculative
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output logic [63:0] vaddr_o, // virtual address out
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output logic valid_o, // signals a valid read
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output exception_t ex_o, // we've encountered an exception
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output logic miss_o, // we missed on the cache
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AXI_BUS.Master axi,
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// Address translation
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output logic fetch_req_o,
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output logic [63:0] fetch_vaddr_o,
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input logic fetch_valid_i,
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input logic [63:0] fetch_paddr_i,
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input exception_t fetch_exception_i
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);
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localparam int unsigned BYTE_OFFSET = $clog2(CACHE_LINE_WIDTH/8); // 3
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localparam int unsigned ICACHE_NUM_WORD = 2**(INDEX_WIDTH - BYTE_OFFSET);
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localparam int unsigned NR_AXI_REFILLS = ($clog2(CACHE_LINE_WIDTH/64) == 0) ? 1 : $clog2(CACHE_LINE_WIDTH/64);
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// registers
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enum logic [3:0] { FLUSH, IDLE, TAG_CMP, WAIT_AXI_R_RESP, WAIT_KILLED_REFILL, WAIT_KILLED_AXI_R_RESP,
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REDO_REQ, WAIT_TAG_SAVED, REFILL
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REDO_REQ, TAG_CMP_SAVED, REFILL,
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WAIT_ADDRESS_TRANSLATION, WAIT_ADDRESS_TRANSLATION_KILLED
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} state_d, state_q;
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logic [$clog2(ICACHE_NUM_WORD)-1:0] cnt_d, cnt_q;
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logic [NR_AXI_REFILLS-1:0] burst_cnt_d, burst_cnt_q; // counter for AXI transfers
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@ -187,6 +197,8 @@ module icache #(
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assign data_be = be;
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assign data_wdata = wdata;
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assign ex_o = fetch_exception_i;
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// ------------------
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// Cache Ctrl
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// ------------------
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@ -211,13 +223,16 @@ module icache #(
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wdata = '0;
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tag_wdata = '0;
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ready_o = 1'b0;
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tag = vaddr_q[TAG_WIDTH+INDEX_WIDTH-1:INDEX_WIDTH];
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tag = fetch_paddr_i[TAG_WIDTH+INDEX_WIDTH-1:INDEX_WIDTH];
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valid_o = 1'b0;
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update_lfsr = 1'b0;
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miss_o = 1'b0;
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axi.ar_valid = 1'b0;
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axi.ar_addr = '0;
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axi.ar_valid = 1'b0;
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axi.ar_addr = '0;
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fetch_req_o = 1'b0;
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fetch_vaddr_o = vaddr_q;
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case (state_q)
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// ~> we are ready to receive a new request
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@ -227,7 +242,7 @@ module icache #(
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if (req_i) begin
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// request the content of all arrays
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req = '1;
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// save the index
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// save the virtual address
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vaddr_d = vaddr_i;
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spec_d = is_speculative_i;
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state_d = TAG_CMP;
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@ -241,11 +256,15 @@ module icache #(
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state_d = IDLE;
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end
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// ~> compare the tag
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TAG_CMP: begin
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TAG_CMP, TAG_CMP_SAVED: begin
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fetch_req_o = 1'b1; // request address translation
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// use the saved tag
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if (state_q == TAG_CMP_SAVED)
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tag = tag_q;
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// -------
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// Hit
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// -------
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if (|hit) begin
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if (|hit && fetch_valid_i) begin
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ready_o = 1'b1;
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valid_o = 1'b1;
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// we've got another request
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@ -255,6 +274,7 @@ module icache #(
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// save the index and stay in compare mode
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vaddr_d = vaddr_i;
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spec_d = is_speculative_i;
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state_d = TAG_CMP;
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// no new request -> go back to idle
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end else begin
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state_d = IDLE;
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@ -269,7 +289,7 @@ module icache #(
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state_d = REFILL;
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evict_way_d = '0;
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// save tag
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tag_d = vaddr_q[TAG_WIDTH+INDEX_WIDTH-1:INDEX_WIDTH];
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tag_d = fetch_paddr_i[TAG_WIDTH+INDEX_WIDTH-1:INDEX_WIDTH];
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miss_o = 1'b1;
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// get way which to replace
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if (repl_w_random) begin
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@ -280,6 +300,28 @@ module icache #(
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evict_way_d[repl_invalid] = 1'b1;
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end
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end
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// if we didn't hit on the TLB we need to wait until the request has been completed
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if (!fetch_valid_i) begin
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state_d = WAIT_ADDRESS_TRANSLATION;
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end
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end
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// ~> wait here for a valid address translation, or on a translation even if the request has been killed
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WAIT_ADDRESS_TRANSLATION, WAIT_ADDRESS_TRANSLATION_KILLED: begin
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fetch_req_o = 1'b1;
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// retry the request if no exception occurred
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if (fetch_valid_i && (state_q == WAIT_ADDRESS_TRANSLATION)) begin
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if (fetch_exception_i.valid)
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valid_o = 1'b1;
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else begin
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state_d = REDO_REQ;
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tag_d = fetch_paddr_i[TAG_WIDTH+INDEX_WIDTH-1:INDEX_WIDTH];
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end
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end else if (fetch_valid_i) begin
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state_d = IDLE;
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end
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if (kill_s2_i)
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state_d = WAIT_ADDRESS_TRANSLATION_KILLED;
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end
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// ~> request a cache-line refill
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REFILL, WAIT_KILLED_REFILL: begin
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@ -326,33 +368,7 @@ module icache #(
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req = '1;
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addr = vaddr_q[INDEX_WIDTH-1:BYTE_OFFSET];
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tag = tag_q;
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state_d = WAIT_TAG_SAVED;
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end
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// we already saved the tag -> apply it
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WAIT_TAG_SAVED: begin
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tag = tag_q;
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state_d = IDLE;
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valid_o = 1'b1;
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// TODO: Check if this is necessary in a real payload environment
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// we can handle a new request here
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ready_o = 1'b1;
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// we are getting a new request
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if (req_i) begin
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// request the content of all arrays
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req = '1;
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// save the index
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vaddr_d = vaddr_i;
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spec_d = is_speculative_i;
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state_d = TAG_CMP;
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end
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if (kill_s1_i)
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state_d = IDLE;
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// go to flushing state
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if (flush_i || flushing_q)
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state_d = FLUSH;
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state_d = TAG_CMP_SAVED; // do tag comparison on the saved tag
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end
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// we need to wait for some AXI responses to come back
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// here for the AW valid
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@ -387,7 +403,11 @@ module icache #(
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if (flush_i) begin
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flushing_d = 1'b1;
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ready_o = 1'b0; // we are not ready to accept a further request here
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end
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// if we are going to flush -> do not accept any new requests
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if (flushing_q)
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ready_o = 1'b0;
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end
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ff1 #(
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@ -224,7 +224,7 @@ module mmu #(
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// ---------
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// watch out for exceptions happening during walking the page table
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if (ptw_active && walking_instr) begin
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fetch_valid_o = 1'b1;
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fetch_valid_o = ptw_error;
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fetch_exception_o = {INSTR_PAGE_FAULT, {25'b0, update_vaddr}, 1'b1};
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end
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end
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