testharness: Add delay to debug_req signal (fixes #211)

Upon start the `debug_req` signal is being delayed for a couple of
cycles to give the core enough time to initialize `a0` and `a1` with its
`hartid` and a pointer to the `dts` (e.g. executing the first
instructions of the ZSBL). This fixes issue #211.

CHANGELOG.md

@@ -8,6 +8,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 
 ### Changed
 
+- Fix RISC-V PK simulation bug caused due to insufficient time to init the `a0` and `a1` registers via the bootrom
 - Fix bug in wt_axi_adapter (only appeared when dcache lines were wider than icache lines)
 - Fix potentially long timing path in `axi_lite_interface`
 - Fix VCS elab warning in `load_store_unit`

src/util/sram.sv

@@ -58,12 +58,9 @@ generate
           .ADDR_WIDTH($clog2(NUM_WORDS)),
           .DATA_DEPTH(NUM_WORDS),
           .OUT_REGS (0),
-// initialize to zero if we want to co-simulate with Spike
-`ifdef SPIKE_TANDEM
+          // this initializes the memory with 0es. adjust to taste...
+          // 0: no init, 1: zero init, 2: random init, 3: deadbeef init
           .SIM_INIT (1)
-`else
-          .SIM_INIT (2)
-`endif
         ) i_ram (
            .Clk_CI    ( clk_i                     ),
            .Rst_RBI   ( rst_ni                    ),