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Add basic assembly test

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This commit is contained in:
Florian Zaruba 2017-05-08 17:59:48 +02:00
parent fc6f5356fb
commit 6cb97a53c9
5 changed files with 48 additions and 10 deletions
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18
src/id_stage.sv
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@ -92,18 +92,18 @@ module id_stage #(
assign ready_o = ~full;
decoder decoder_i (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.pc_i ( pc_if_i ),
.is_compressed_i ( is_compressed_i ),
.instruction_i ( instruction_i ),
.ex_i ( ex_if_i ),
.instruction_o ( decoded_instr_dc_sb )
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
.pc_i ( pc_if_i ),
.is_compressed_i ( is_compressed_i ),
.instruction_i ( instruction_i ),
.ex_i ( ex_if_i ),
.instruction_o ( decoded_instr_dc_sb )
);
scoreboard #(
.NR_ENTRIES ( NR_ENTRIES ),
.NR_WB_PORTS ( NR_WB_PORTS )
.NR_ENTRIES ( NR_ENTRIES ),
.NR_WB_PORTS ( NR_WB_PORTS )
)
scoreboard_i
(

2
src/issue_read_operands.sv
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@ -193,7 +193,7 @@ module issue_read_operands (
operand_a_n = {52'b0, issue_instr_i.rs1};
end
// or is it an immediate (including PC), this is not the case for a store
if (issue_instr_i.use_imm && (issue_instr_i.op inside {SD, SW, SH, SB})) begin
if (issue_instr_i.use_imm && ~(issue_instr_i.op inside {SD, SW, SH, SB})) begin
operand_b_n = issue_instr_i.result;
end
// immediates are the third operands in the store case

1
test/.gitignore vendored Normal file
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@ -0,0 +1 @@
*.v

21
test/Makefile Normal file
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@ -0,0 +1,21 @@
CC = riscv64-unknown-elf-gcc
OBJDUMP = riscv64-unknown-elf-objdump
ODFLAGS =
OBJCOPY = riscv64-unknown-elf-objcopy
OCFLAGS =
ASFLAGS = -c
CFLAGS =
LDFLAGS =
TESTS = add_test
.S.o:
$(CC) $(ASFLAGS) -o $@ $<
# .c.o:
# $(CC) $(CFLAGS) -o $@ -c $<
# .v: .S.o
$(TESTS): $(TESTS).o
$(OBJCOPY) -O verilog -I elf64-little $< $@.v

16
test/add_test.S Executable file
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@ -0,0 +1,16 @@
.text
nop
nop
nop
addi x1, x0, 1
addi x2, x0, 1
add x3, x1, x2
add x4, x2, x3
add x5, x3, x4
add x6, x4, x5
add x7, x5, x6
add x8, x6, x7
add x9, x7, x8
nop
nop
nop