mirror of
https://github.com/openhwgroup/cva6.git
synced 2025-04-17 19:04:48 -04:00
Altera fpga update (#2790)
Update Altera APU design to support linux in both 32 and 64 bits * Move JTAG UART inside peripherals to properly connect the interruput request to PLIC * Reduce the frequency of operation to 100MHz to avoid timing issues in 64bit version * Update UART read and write operation in bootrom to allow keyboard interrupt
This commit is contained in:
AngelaGonzalezMarino
GitHub
parent
bac134b7b5
commit
6e0cf8d730
4 changed files with 128 additions and 251 deletions
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@ -143,7 +143,7 @@ proc do_create_io_pll {} {
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set_instance_parameter_value iopll_0 {gui_new_mif_file_path} {~/pll.mif}
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set_instance_parameter_value iopll_0 {gui_number_of_clocks} {5}
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set_instance_parameter_value iopll_0 {gui_operation_mode} {direct}
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set_instance_parameter_value iopll_0 {gui_output_clock_frequency0} {200.0}
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set_instance_parameter_value iopll_0 {gui_output_clock_frequency0} {100.0}
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set_instance_parameter_value iopll_0 {gui_output_clock_frequency1} {125.0}
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set_instance_parameter_value iopll_0 {gui_output_clock_frequency10} {100.0}
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set_instance_parameter_value iopll_0 {gui_output_clock_frequency11} {100.0}
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@ -161,7 +161,7 @@ proc do_create_io_pll {} {
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set_instance_parameter_value iopll_0 {gui_output_clock_frequency7} {100.0}
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set_instance_parameter_value iopll_0 {gui_output_clock_frequency8} {100.0}
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set_instance_parameter_value iopll_0 {gui_output_clock_frequency9} {100.0}
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set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps0} {5000.0}
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set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps0} {10000.0}
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set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps1} {8000.0}
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set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps10} {10000.0}
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set_instance_parameter_value iopll_0 {gui_output_clock_frequency_ps11} {10000.0}
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@ -437,60 +437,60 @@ if (CVA6Cfg.XLEN==32 ) begin
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end else begin
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assign master[ariane_soc::Debug].aw_id = master_to_dm[0].aw_id;
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assign master[ariane_soc::Debug].aw_addr = master_to_dm[0].aw_addr;
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assign master[ariane_soc::Debug].aw_len = master_to_dm[0].aw_len;
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assign master[ariane_soc::Debug].aw_size = master_to_dm[0].aw_size;
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assign master[ariane_soc::Debug].aw_burst = master_to_dm[0].aw_burst;
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assign master[ariane_soc::Debug].aw_lock = master_to_dm[0].aw_lock;
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assign master[ariane_soc::Debug].aw_cache = master_to_dm[0].aw_cache;
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assign master[ariane_soc::Debug].aw_prot = master_to_dm[0].aw_prot;
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assign master[ariane_soc::Debug].aw_qos = master_to_dm[0].aw_qos;
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assign master[ariane_soc::Debug].aw_atop = master_to_dm[0].aw_atop;
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assign master[ariane_soc::Debug].aw_region = master_to_dm[0].aw_region;
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assign master[ariane_soc::Debug].aw_user = master_to_dm[0].aw_user;
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assign master[ariane_soc::Debug].aw_valid = master_to_dm[0].aw_valid;
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assign master_to_dm[0].aw_id = master[ariane_soc::Debug].aw_id;
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assign master_to_dm[0].aw_addr = master[ariane_soc::Debug].aw_addr;
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assign master_to_dm[0].aw_len = master[ariane_soc::Debug].aw_len;
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assign master_to_dm[0].aw_size = master[ariane_soc::Debug].aw_size;
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assign master_to_dm[0].aw_burst= master[ariane_soc::Debug].aw_burst;
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assign master_to_dm[0].aw_lock = master[ariane_soc::Debug].aw_lock;
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assign master_to_dm[0].aw_cache= master[ariane_soc::Debug].aw_cache;
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assign master_to_dm[0].aw_prot = master[ariane_soc::Debug].aw_prot;
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assign master_to_dm[0].aw_qos = master[ariane_soc::Debug].aw_qos;
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assign master_to_dm[0].aw_atop = master[ariane_soc::Debug].aw_atop;
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assign master_to_dm[0].aw_region = master[ariane_soc::Debug].aw_region;
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assign master_to_dm[0].aw_user = master[ariane_soc::Debug].aw_user;
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assign master_to_dm[0].aw_valid= master[ariane_soc::Debug].aw_valid;
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assign master_to_dm[0].aw_ready =master[ariane_soc::Debug].aw_ready;
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assign master[ariane_soc::Debug].aw_ready = master_to_dm[0].aw_ready;
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assign master[ariane_soc::Debug].w_data = master_to_dm[0].w_data;
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assign master[ariane_soc::Debug].w_strb = master_to_dm[0].w_strb;
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assign master[ariane_soc::Debug].w_last = master_to_dm[0].w_last;
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assign master[ariane_soc::Debug].w_user = master_to_dm[0].w_user;
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assign master[ariane_soc::Debug].w_valid = master_to_dm[0].w_valid;
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assign master_to_dm[0].w_data = master[ariane_soc::Debug].w_data;
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assign master_to_dm[0].w_strb = master[ariane_soc::Debug].w_strb;
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assign master_to_dm[0].w_last = master[ariane_soc::Debug].w_last;
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assign master_to_dm[0].w_user = master[ariane_soc::Debug].w_user;
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assign master_to_dm[0].w_valid= master[ariane_soc::Debug].w_valid;
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assign master_to_dm[0].w_ready =master[ariane_soc::Debug].w_ready;
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assign master[ariane_soc::Debug].w_ready = master_to_dm[0].w_ready;
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assign master_to_dm[0].b_id =master[ariane_soc::Debug].b_id;
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assign master_to_dm[0].b_resp =master[ariane_soc::Debug].b_resp;
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assign master_to_dm[0].b_user =master[ariane_soc::Debug].b_user;
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assign master_to_dm[0].b_valid =master[ariane_soc::Debug].b_valid;
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assign master[ariane_soc::Debug].b_id = master_to_dm[0].b_id;
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assign master[ariane_soc::Debug].b_resp = master_to_dm[0].b_resp;
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assign master[ariane_soc::Debug].b_user = master_to_dm[0].b_user;
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assign master[ariane_soc::Debug].b_valid= master_to_dm[0].b_valid;
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assign master[ariane_soc::Debug].b_ready = master_to_dm[0].b_ready;
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assign master_to_dm[0].b_ready = master[ariane_soc::Debug].b_ready;
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assign master[ariane_soc::Debug].ar_id = master_to_dm[0].ar_id;
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assign master[ariane_soc::Debug].ar_addr = master_to_dm[0].ar_addr;
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assign master[ariane_soc::Debug].ar_len = master_to_dm[0].ar_len;
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assign master[ariane_soc::Debug].ar_size = master_to_dm[0].ar_size;
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assign master[ariane_soc::Debug].ar_burst = master_to_dm[0].ar_burst;
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assign master[ariane_soc::Debug].ar_lock = master_to_dm[0].ar_lock;
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assign master[ariane_soc::Debug].ar_cache = master_to_dm[0].ar_cache;
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assign master[ariane_soc::Debug].ar_prot = master_to_dm[0].ar_prot;
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assign master[ariane_soc::Debug].ar_qos = master_to_dm[0].ar_qos;
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assign master[ariane_soc::Debug].ar_region = master_to_dm[0].ar_region;
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assign master[ariane_soc::Debug].ar_user = master_to_dm[0].ar_user;
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assign master[ariane_soc::Debug].ar_valid = master_to_dm[0].ar_valid;
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assign master_to_dm[0].ar_id = master[ariane_soc::Debug].ar_id;
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assign master_to_dm[0].ar_addr = master[ariane_soc::Debug].ar_addr;
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assign master_to_dm[0].ar_len = master[ariane_soc::Debug].ar_len;
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assign master_to_dm[0].ar_size = master[ariane_soc::Debug].ar_size;
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assign master_to_dm[0].ar_burst = master[ariane_soc::Debug].ar_burst;
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assign master_to_dm[0].ar_lock = master[ariane_soc::Debug].ar_lock;
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assign master_to_dm[0].ar_cache = master[ariane_soc::Debug].ar_cache;
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assign master_to_dm[0].ar_prot = master[ariane_soc::Debug].ar_prot;
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assign master_to_dm[0].ar_qos = master[ariane_soc::Debug].ar_qos;
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assign master_to_dm[0].ar_region = master[ariane_soc::Debug].ar_region;
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assign master_to_dm[0].ar_user = master[ariane_soc::Debug].ar_user;
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assign master_to_dm[0].ar_valid = master[ariane_soc::Debug].ar_valid;
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assign master_to_dm[0].ar_ready =master[ariane_soc::Debug].ar_ready;
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assign master[ariane_soc::Debug].ar_ready = master_to_dm[0].ar_ready;
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assign master_to_dm[0].r_id =master[ariane_soc::Debug].r_id;
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assign master_to_dm[0].r_data =master[ariane_soc::Debug].r_data;
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assign master_to_dm[0].r_resp =master[ariane_soc::Debug].r_resp;
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assign master_to_dm[0].r_last =master[ariane_soc::Debug].r_last;
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assign master_to_dm[0].r_user =master[ariane_soc::Debug].r_user;
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assign master_to_dm[0].r_valid =master[ariane_soc::Debug].r_valid;
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assign master[ariane_soc::Debug].r_id = master_to_dm[0].r_id;
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assign master[ariane_soc::Debug].r_data = master_to_dm[0].r_data;
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assign master[ariane_soc::Debug].r_resp = master_to_dm[0].r_resp;
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assign master[ariane_soc::Debug].r_last = master_to_dm[0].r_last;
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assign master[ariane_soc::Debug].r_user = master_to_dm[0].r_user;
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assign master[ariane_soc::Debug].r_valid = master_to_dm[0].r_valid;
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assign master[ariane_soc::Debug].r_ready = master_to_dm[0].r_ready;
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assign master_to_dm[0].r_ready = master[ariane_soc::Debug].r_ready;
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end
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@ -744,19 +744,13 @@ end
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logic clk_200MHz_ref;
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AXI_BUS #(
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.AXI_ADDR_WIDTH ( AxiAddrWidth ),
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.AXI_DATA_WIDTH ( AxiDataWidth ),
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.AXI_ID_WIDTH ( AxiIdWidthSlaves ),
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.AXI_USER_WIDTH ( AxiUserWidth )
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) uart_bus();
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cva6_peripherals #(
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.AxiAddrWidth ( AxiAddrWidth ),
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.AxiDataWidth ( AxiDataWidth ),
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.AxiIdWidth ( AxiIdWidthSlaves ),
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.AxiUserWidth ( AxiUserWidth ),
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.InclUART ( 1'b0 ),
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.InclUART ( 1'b1 ),
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.InclGPIO ( 1'b1 ),
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.InclSPI ( 1'b0 ),
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.InclEthernet ( 1'b0 )
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@ -765,8 +759,7 @@ cva6_peripherals #(
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.clk_200MHz_i ( clk_200MHz_ref ),
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.rst_ni ( ndmreset_n ),
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.plic ( master[ariane_soc::PLIC] ),
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// .uart ( master[ariane_soc::UART] ),
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.uart ( uart_bus ),
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.uart ( master[ariane_soc::UART] ),
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.spi ( master[ariane_soc::SPI] ),
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.gpio ( master[ariane_soc::GPIO] ),
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.eth_clk_i ( eth_clk ),
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@ -797,84 +790,6 @@ cva6_peripherals #(
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// UART Through JTAG//
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logic uart_amm_ready;
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logic uart_amm_read;
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logic uart_amm_write;
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logic uart_amm_read_n;
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logic uart_amm_write_n;
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logic uart_amm_chipselect;
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logic uart_amm_irq;
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logic [0:0] uart_amm_address;
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logic [31:0] uart_amm_rdata;
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logic [31:0] uart_amm_wdata;
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assign uart_amm_read_n = ~uart_amm_read;
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assign uart_amm_write_n = ~uart_amm_write;
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cva6_intel_jtag_uart_0 uart_i (
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.clk (clk), // input, width = 1, clk.clk
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.rst_n (ndmreset_n), // input, width = 1, reset.reset_n
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.av_chipselect (uart_amm_chipselect), // input, width = 1, avalon_jtag_slave.chipselect
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.av_address (uart_amm_address), // input, width = 1, .address
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.av_read_n (uart_amm_read_n), // input, width = 1, .read_n
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.av_readdata (uart_amm_rdata), // output, width = 32, .readdata
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.av_write_n (uart_amm_write_n), // input, width = 1, .write_n
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.av_writedata (uart_amm_wdata), // input, width = 32, .writedata
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.av_waitrequest (uart_amm_ready), // output, width = 1, .waitrequest
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.av_irq (uart_amm_irq) // output, width = 1, irq.irq
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);
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//axi4 to avalon converter
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interconnect_altera_mm_interconnect_1920_v5r556a axi_to_avalon_uart (
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.axi_bridge_1_m0_awid (master[ariane_soc::UART].aw_id), // input, width = 8, axi_bridge_1_m0.awid
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.axi_bridge_1_m0_awaddr (master[ariane_soc::UART].aw_addr), // input, width = 64, .awaddr
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.axi_bridge_1_m0_awlen (master[ariane_soc::UART].aw_len), // input, width = 8, .awlen
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.axi_bridge_1_m0_awsize (master[ariane_soc::UART].aw_size), // input, width = 3, .awsize
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.axi_bridge_1_m0_awburst (master[ariane_soc::UART].aw_burst), // input, width = 2, .awburst
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.axi_bridge_1_m0_awlock (master[ariane_soc::UART].aw_lock), // input, width = 1, .awlock
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.axi_bridge_1_m0_awcache (master[ariane_soc::UART].aw_cache), // input, width = 4, .awcache
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.axi_bridge_1_m0_awprot (master[ariane_soc::UART].aw_prot), // input, width = 3, .awprot
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.axi_bridge_1_m0_awvalid (master[ariane_soc::UART].aw_valid), // input, width = 1, .awvalid
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.axi_bridge_1_m0_awready (master[ariane_soc::UART].aw_ready), // output, width = 1, .awready
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.axi_bridge_1_m0_wdata (master[ariane_soc::UART].w_data), // input, width = 64, .wdata
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.axi_bridge_1_m0_wstrb (master[ariane_soc::UART].w_strb), // input, width = 8, .wstrb
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.axi_bridge_1_m0_wlast (master[ariane_soc::UART].w_last), // input, width = 1, .wlast
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.axi_bridge_1_m0_wvalid (master[ariane_soc::UART].w_valid), // input, width = 1, .wvalid
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.axi_bridge_1_m0_wready (master[ariane_soc::UART].w_ready), // output, width = 1, .wready
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.axi_bridge_1_m0_bid (master[ariane_soc::UART].b_id), // output, width = 8, .bid
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.axi_bridge_1_m0_bresp (master[ariane_soc::UART].b_resp), // output, width = 2, .bresp
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.axi_bridge_1_m0_bvalid (master[ariane_soc::UART].b_valid), // output, width = 1, .bvalid
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.axi_bridge_1_m0_bready (master[ariane_soc::UART].b_ready), // input, width = 1, .bready
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.axi_bridge_1_m0_arid (master[ariane_soc::UART].ar_id), // input, width = 8, .arid
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.axi_bridge_1_m0_araddr (master[ariane_soc::UART].ar_addr), // input, width = 64, .araddr
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.axi_bridge_1_m0_arlen (master[ariane_soc::UART].ar_len), // input, width = 8, .arlen
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.axi_bridge_1_m0_arsize (master[ariane_soc::UART].ar_size), // input, width = 3, .arsize
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.axi_bridge_1_m0_arburst (master[ariane_soc::UART].ar_burst), // input, width = 2, .arburst
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.axi_bridge_1_m0_arlock (master[ariane_soc::UART].ar_lock), // input, width = 1, .arlock
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.axi_bridge_1_m0_arcache (master[ariane_soc::UART].ar_cache), // input, width = 4, .arcache
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.axi_bridge_1_m0_arprot (master[ariane_soc::UART].ar_prot), // input, width = 3, .arprot
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.axi_bridge_1_m0_arvalid (master[ariane_soc::UART].ar_valid), // input, width = 1, .arvalid
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.axi_bridge_1_m0_arready (master[ariane_soc::UART].ar_ready), // output, width = 1, .arready
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.axi_bridge_1_m0_rid (master[ariane_soc::UART].r_id), // output, width = 8, .rid
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.axi_bridge_1_m0_rdata (master[ariane_soc::UART].r_data), // output, width = 64, .rdata
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.axi_bridge_1_m0_rresp (master[ariane_soc::UART].r_resp), // output, width = 2, .rresp
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.axi_bridge_1_m0_rlast (master[ariane_soc::UART].r_last), // output, width = 1, .rlast
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.axi_bridge_1_m0_rvalid (master[ariane_soc::UART].r_valid), // output, width = 1, .rvalid
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.axi_bridge_1_m0_rready (master[ariane_soc::UART].r_ready), // input, width = 1, .rready
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.jtag_uart_0_avalon_jtag_slave_address (uart_amm_address), // output, width = 1, jtag_uart_0_avalon_jtag_slave.address
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.jtag_uart_0_avalon_jtag_slave_write (uart_amm_write), // output, width = 1, .write
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.jtag_uart_0_avalon_jtag_slave_read (uart_amm_read), // output, width = 1, .read
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.jtag_uart_0_avalon_jtag_slave_readdata (uart_amm_rdata), // input, width = 32, .readdata
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.jtag_uart_0_avalon_jtag_slave_writedata (uart_amm_wdata), // output, width = 32, .writedata
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.jtag_uart_0_avalon_jtag_slave_waitrequest (uart_amm_ready), // input, width = 1, .waitrequest
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.jtag_uart_0_avalon_jtag_slave_chipselect (uart_amm_chipselect), // output, width = 1, .chipselect
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.axi_bridge_1_clk_reset_reset_bridge_in_reset_reset (~ndmreset_n), // input, width = 1, axi_bridge_1_clk_reset_reset_bridge_in_reset.reset
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.axi_bridge_1_m0_translator_clk_reset_reset_bridge_in_reset_reset (~ndmreset_n), // input, width = 1, axi_bridge_1_m0_translator_clk_reset_reset_bridge_in_reset.reset
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.emif_fm_0_emif_usr_clk_clk (clk) // input, width = 1, emif_fm_0_emif_usr_clk.clk
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);
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// ---------------------
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// Board peripherals
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@ -192,123 +192,85 @@ module cva6_peripherals #(
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// ---------------
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// 2. UART
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// ---------------
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logic uart_penable;
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logic uart_pwrite;
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logic [31:0] uart_paddr;
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logic uart_psel;
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logic [31:0] uart_pwdata;
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logic [31:0] uart_prdata;
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logic uart_pready;
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logic uart_pslverr;
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axi2apb_64_32 #(
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.AXI4_ADDRESS_WIDTH ( AxiAddrWidth ),
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.AXI4_RDATA_WIDTH ( AxiDataWidth ),
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.AXI4_WDATA_WIDTH ( AxiDataWidth ),
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.AXI4_ID_WIDTH ( AxiIdWidth ),
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.AXI4_USER_WIDTH ( AxiUserWidth ),
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.BUFF_DEPTH_SLAVE ( 2 ),
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.APB_ADDR_WIDTH ( 32 )
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) i_axi2apb_64_32_uart (
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.ACLK ( clk_i ),
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.ARESETn ( rst_ni ),
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.test_en_i ( 1'b0 ),
|
||||
.AWID_i ( uart.aw_id ),
|
||||
.AWADDR_i ( uart.aw_addr ),
|
||||
.AWLEN_i ( uart.aw_len ),
|
||||
.AWSIZE_i ( uart.aw_size ),
|
||||
.AWBURST_i ( uart.aw_burst ),
|
||||
.AWLOCK_i ( uart.aw_lock ),
|
||||
.AWCACHE_i ( uart.aw_cache ),
|
||||
.AWPROT_i ( uart.aw_prot ),
|
||||
.AWREGION_i( uart.aw_region ),
|
||||
.AWUSER_i ( uart.aw_user ),
|
||||
.AWQOS_i ( uart.aw_qos ),
|
||||
.AWVALID_i ( uart.aw_valid ),
|
||||
.AWREADY_o ( uart.aw_ready ),
|
||||
.WDATA_i ( uart.w_data ),
|
||||
.WSTRB_i ( uart.w_strb ),
|
||||
.WLAST_i ( uart.w_last ),
|
||||
.WUSER_i ( uart.w_user ),
|
||||
.WVALID_i ( uart.w_valid ),
|
||||
.WREADY_o ( uart.w_ready ),
|
||||
.BID_o ( uart.b_id ),
|
||||
.BRESP_o ( uart.b_resp ),
|
||||
.BVALID_o ( uart.b_valid ),
|
||||
.BUSER_o ( uart.b_user ),
|
||||
.BREADY_i ( uart.b_ready ),
|
||||
.ARID_i ( uart.ar_id ),
|
||||
.ARADDR_i ( uart.ar_addr ),
|
||||
.ARLEN_i ( uart.ar_len ),
|
||||
.ARSIZE_i ( uart.ar_size ),
|
||||
.ARBURST_i ( uart.ar_burst ),
|
||||
.ARLOCK_i ( uart.ar_lock ),
|
||||
.ARCACHE_i ( uart.ar_cache ),
|
||||
.ARPROT_i ( uart.ar_prot ),
|
||||
.ARREGION_i( uart.ar_region ),
|
||||
.ARUSER_i ( uart.ar_user ),
|
||||
.ARQOS_i ( uart.ar_qos ),
|
||||
.ARVALID_i ( uart.ar_valid ),
|
||||
.ARREADY_o ( uart.ar_ready ),
|
||||
.RID_o ( uart.r_id ),
|
||||
.RDATA_o ( uart.r_data ),
|
||||
.RRESP_o ( uart.r_resp ),
|
||||
.RLAST_o ( uart.r_last ),
|
||||
.RUSER_o ( uart.r_user ),
|
||||
.RVALID_o ( uart.r_valid ),
|
||||
.RREADY_i ( uart.r_ready ),
|
||||
.PENABLE ( uart_penable ),
|
||||
.PWRITE ( uart_pwrite ),
|
||||
.PADDR ( uart_paddr ),
|
||||
.PSEL ( uart_psel ),
|
||||
.PWDATA ( uart_pwdata ),
|
||||
.PRDATA ( uart_prdata ),
|
||||
.PREADY ( uart_pready ),
|
||||
.PSLVERR ( uart_pslverr )
|
||||
);
|
||||
// UART Through JTAG//
|
||||
|
||||
if (InclUART) begin : gen_uart
|
||||
apb_uart i_apb_uart (
|
||||
.CLK ( clk_i ),
|
||||
.RSTN ( rst_ni ),
|
||||
.PSEL ( uart_psel ),
|
||||
.PENABLE ( uart_penable ),
|
||||
.PWRITE ( uart_pwrite ),
|
||||
.PADDR ( uart_paddr[4:2] ),
|
||||
.PWDATA ( uart_pwdata ),
|
||||
.PRDATA ( uart_prdata ),
|
||||
.PREADY ( uart_pready ),
|
||||
.PSLVERR ( uart_pslverr ),
|
||||
.INT ( irq_sources[0] ),
|
||||
.OUT1N ( ), // keep open
|
||||
.OUT2N ( ), // keep open
|
||||
.RTSN ( ), // no flow control
|
||||
.DTRN ( ), // no flow control
|
||||
.CTSN ( 1'b0 ),
|
||||
.DSRN ( 1'b0 ),
|
||||
.DCDN ( 1'b0 ),
|
||||
.RIN ( 1'b0 ),
|
||||
.SIN ( rx_i ),
|
||||
.SOUT ( tx_o )
|
||||
);
|
||||
end else begin
|
||||
/* pragma translate_off */
|
||||
`ifndef VERILATOR
|
||||
mock_uart i_mock_uart (
|
||||
.clk_i ( clk_i ),
|
||||
.rst_ni ( rst_ni ),
|
||||
.penable_i ( uart_penable ),
|
||||
.pwrite_i ( uart_pwrite ),
|
||||
.paddr_i ( uart_paddr ),
|
||||
.psel_i ( uart_psel ),
|
||||
.pwdata_i ( uart_pwdata ),
|
||||
.prdata_o ( uart_prdata ),
|
||||
.pready_o ( uart_pready ),
|
||||
.pslverr_o ( uart_pslverr )
|
||||
);
|
||||
`endif
|
||||
/* pragma translate_on */
|
||||
end
|
||||
logic uart_amm_ready;
|
||||
logic uart_amm_read;
|
||||
logic uart_amm_write;
|
||||
logic uart_amm_read_n;
|
||||
logic uart_amm_write_n;
|
||||
logic uart_amm_chipselect;
|
||||
logic uart_amm_irq;
|
||||
logic [0:0] uart_amm_address;
|
||||
logic [31:0] uart_amm_rdata;
|
||||
logic [31:0] uart_amm_wdata;
|
||||
|
||||
|
||||
assign uart_amm_read_n = ~uart_amm_read;
|
||||
assign uart_amm_write_n = ~uart_amm_write;
|
||||
|
||||
cva6_intel_jtag_uart_0 uart_i (
|
||||
.clk (clk_i), // input, width = 1, clk.clk
|
||||
.rst_n (rst_ni),
|
||||
.av_chipselect (uart_amm_chipselect), // input, width = 1, avalon_jtag_slave.chipselect
|
||||
.av_address (uart_amm_address), // input, width = 1, .address
|
||||
.av_read_n (uart_amm_read_n), // input, width = 1, .read_n
|
||||
.av_readdata (uart_amm_rdata), // output, width = 32, .readdata
|
||||
.av_write_n (uart_amm_write_n), // input, width = 1, .write_n
|
||||
.av_writedata (uart_amm_wdata), // input, width = 32, .writedata
|
||||
.av_waitrequest (uart_amm_ready), // output, width = 1, .waitrequest
|
||||
.av_irq (irq_sources[0]) // output, width = 1, irq.irq
|
||||
);
|
||||
|
||||
//axi4 to avalon converter
|
||||
interconnect_altera_mm_interconnect_1920_v5r556a axi_to_avalon_uart (
|
||||
.axi_bridge_1_m0_awid (uart.aw_id), // input, width = 8, axi_bridge_1_m0.awid
|
||||
.axi_bridge_1_m0_awaddr (uart.aw_addr), // input, width = 64, .awaddr
|
||||
.axi_bridge_1_m0_awlen (uart.aw_len), // input, width = 8, .awlen
|
||||
.axi_bridge_1_m0_awsize (uart.aw_size), // input, width = 3, .awsize
|
||||
.axi_bridge_1_m0_awburst (uart.aw_burst), // input, width = 2, .awburst
|
||||
.axi_bridge_1_m0_awlock (uart.aw_lock), // input, width = 1, .awlock
|
||||
.axi_bridge_1_m0_awcache (uart.aw_cache), // input, width = 4, .awcache
|
||||
.axi_bridge_1_m0_awprot (uart.aw_prot), // input, width = 3, .awprot
|
||||
.axi_bridge_1_m0_awvalid (uart.aw_valid), // input, width = 1, .awvalid
|
||||
.axi_bridge_1_m0_awready (uart.aw_ready), // output, width = 1, .awready
|
||||
.axi_bridge_1_m0_wdata (uart.w_data), // input, width = 64, .wdata
|
||||
.axi_bridge_1_m0_wstrb (uart.w_strb), // input, width = 8, .wstrb
|
||||
.axi_bridge_1_m0_wlast (uart.w_last), // input, width = 1, .wlast
|
||||
.axi_bridge_1_m0_wvalid (uart.w_valid), // input, width = 1, .wvalid
|
||||
.axi_bridge_1_m0_wready (uart.w_ready), // output, width = 1, .wready
|
||||
.axi_bridge_1_m0_bid (uart.b_id), // output, width = 8, .bid
|
||||
.axi_bridge_1_m0_bresp (uart.b_resp), // output, width = 2, .bresp
|
||||
.axi_bridge_1_m0_bvalid (uart.b_valid), // output, width = 1, .bvalid
|
||||
.axi_bridge_1_m0_bready (uart.b_ready), // input, width = 1, .bready
|
||||
.axi_bridge_1_m0_arid (uart.ar_id), // input, width = 8, .arid
|
||||
.axi_bridge_1_m0_araddr (uart.ar_addr), // input, width = 64, .araddr
|
||||
.axi_bridge_1_m0_arlen (uart.ar_len), // input, width = 8, .arlen
|
||||
.axi_bridge_1_m0_arsize (uart.ar_size), // input, width = 3, .arsize
|
||||
.axi_bridge_1_m0_arburst (uart.ar_burst), // input, width = 2, .arburst
|
||||
.axi_bridge_1_m0_arlock (uart.ar_lock), // input, width = 1, .arlock
|
||||
.axi_bridge_1_m0_arcache (uart.ar_cache), // input, width = 4, .arcache
|
||||
.axi_bridge_1_m0_arprot (uart.ar_prot), // input, width = 3, .arprot
|
||||
.axi_bridge_1_m0_arvalid (uart.ar_valid), // input, width = 1, .arvalid
|
||||
.axi_bridge_1_m0_arready (uart.ar_ready), // output, width = 1, .arready
|
||||
.axi_bridge_1_m0_rid (uart.r_id), // output, width = 8, .rid
|
||||
.axi_bridge_1_m0_rdata (uart.r_data), // output, width = 64, .rdata
|
||||
.axi_bridge_1_m0_rresp (uart.r_resp), // output, width = 2, .rresp
|
||||
.axi_bridge_1_m0_rlast (uart.r_last), // output, width = 1, .rlast
|
||||
.axi_bridge_1_m0_rvalid (uart.r_valid), // output, width = 1, .rvalid
|
||||
.axi_bridge_1_m0_rready (uart.r_ready), // input, width = 1, .rready
|
||||
.jtag_uart_0_avalon_jtag_slave_address (uart_amm_address), // output, width = 1, jtag_uart_0_avalon_jtag_slave.address
|
||||
.jtag_uart_0_avalon_jtag_slave_write (uart_amm_write), // output, width = 1, .write
|
||||
.jtag_uart_0_avalon_jtag_slave_read (uart_amm_read), // output, width = 1, .read
|
||||
.jtag_uart_0_avalon_jtag_slave_readdata (uart_amm_rdata), // input, width = 32, .readdata
|
||||
.jtag_uart_0_avalon_jtag_slave_writedata (uart_amm_wdata), // output, width = 32, .writedata
|
||||
.jtag_uart_0_avalon_jtag_slave_waitrequest (uart_amm_ready), // input, width = 1, .waitrequest
|
||||
.jtag_uart_0_avalon_jtag_slave_chipselect (uart_amm_chipselect), // output, width = 1, .chipselect
|
||||
.axi_bridge_1_clk_reset_reset_bridge_in_reset_reset (~rst_ni), // input, width = 1, axi_bridge_1_clk_reset_reset_bridge_in_reset.reset
|
||||
.axi_bridge_1_m0_translator_clk_reset_reset_bridge_in_reset_reset (~rst_ni), // input, width = 1, axi_bridge_1_m0_translator_clk_reset_reset_bridge_in_reset.reset
|
||||
.emif_fm_0_emif_usr_clk_clk (clk_i) // input, width = 1, emif_fm_0_emif_usr_clk.clk
|
||||
);
|
||||
|
||||
// ---------------
|
||||
// 3. SPI
|
||||
|
|
|
|||
|
|
@ -22,7 +22,7 @@ int is_transmit_empty()
|
|||
|
||||
char is_transmit_empty_altera()
|
||||
{
|
||||
return read_reg_u8(UART_THR+6);
|
||||
return ((read_reg_u8(UART_THR+7) << 8 ) + read_reg_u8(UART_THR+6));
|
||||
}
|
||||
|
||||
int is_receive_empty()
|
||||
|
|
@ -30,7 +30,7 @@ int is_receive_empty()
|
|||
#ifndef PLAT_AGILEX
|
||||
return !(read_reg_u8(UART_LINE_STATUS) & 0x1);
|
||||
#else
|
||||
return !(read_reg_u8(UART_THR+1) & 0x8);
|
||||
return (read_reg_u8(UART_THR) == 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue