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Updated user manual to address several configuration (second pass) (#1696)
This commit is contained in:
Jérôme Quévremont
GitHub
parent
98c776dc2d
commit
6e41bc8b52
12 changed files with 1701 additions and 1411 deletions
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@ -18,6 +18,16 @@
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.. _cva6_csr_performance_counters:
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*Applicability of this chapter to configurations:*
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.. csv-table::
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:widths: auto
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:align: left
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:header: "Configuration", "Implementation"
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"CV32A60X", "Performance counters included"
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"CV32E6?X", "No performance counters"
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CSR performance counters control
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================================
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CVA6 implements performance counters according to the RISC-V Privileged Specification, version 1.11 (see Hardware Performance Monitor, Section 3.1.10). The performance counters are placed inside the Control and Status Registers(CSRs) and can be accessed with the ``CSRRW(I)`` and ``CSRRS/C(I)`` instructions.
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@ -47,7 +47,6 @@ Suggested content:
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FPGA specific guidelines
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------------------------
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Also needed for prototyping of ASICs
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Suggested content:
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* Typical critical paths in FPGA and suggestions for optimizations
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File diff suppressed because it is too large
Load diff
179
docs/01_cva6_user/RISCV_Instructions_RV32A.rst
Normal file
179
docs/01_cva6_user/RISCV_Instructions_RV32A.rst
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@ -0,0 +1,179 @@
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..
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Copyright (c) 2023 OpenHW Group
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Copyright (c) 2023 Thales
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SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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.. Level 1
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=======
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Level 2
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-------
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Level 3
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~~~~~~~
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Level 4
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^^^^^^^
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.. _cva6_riscv_instructions_RV32A:
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*Applicability of this chapter to configurations:*
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.. csv-table::
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:widths: auto
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:align: left
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:header: "Configuration", "Implementation"
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"CV32A60X", "Implemented extension"
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"CV32E6?X", "Not implemented extension"
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**Note**: This chapter is specific to CV32A6 configurations. CV64A6 configurations implement as an option RV64A, that includes additional instructions.
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RV32A Atomic Instructions
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--------------------------------
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The standard atomic instruction extension is denoted by instruction subset name “A”, and contains instructions that atomically read-modify-write memory to support synchronization between
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multiple RISC-V harts running in the same memory space. The two forms of atomic instruction
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provided are load-reserved/store-conditional instructions and atomic fetch-and-op memory instructions. Both types of atomic instruction support various memory consistency orderings including
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unordered, acquire, release, and sequentially consistent semantics.
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Load-Reserved/Store-Conditional Instructions
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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- **LR.W**: Load-Reserved Word
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**Format**: lr.w rd, (rs1)
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**Description**: LR loads a word from the address in rs1, places the sign-extended value in rd, and registers a reservation on the memory address.
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**Pseudocode**: x[rd] = LoadReserved32(M[x[rs1]])
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**Invalid values**: NONE
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**Exception raised**: If the address is not naturally aligned (4-byte boundary), a Load/AMO address misaligned exception will be generated.
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- **SC.W**: Store-Conditional Word
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**Format**: sc.w rd, rs2, (rs1)
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**Description**: SC writes a word in rs2 to the address in rs1, provided a valid reservation still exists on that address. SC writes zero to rd on success or a nonzero code on failure.
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**Pseudocode**: x[rd] = StoreConditional32(M[x[rs1]], x[rs2])
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**Invalid values**: NONE
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**Exception raised**: If the address is not naturally aligned (4-byte boundary), a Store/AMO address misaligned exception will be generated.
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Atomic Memory Operations
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^^^^^^^^^^^^^^^^^^^^^^^^^^
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- **AMOADD.W**: Atomic Memory Operation: Add Word
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**Format**: amoadd.w rd, rs2, (rs1)
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**Description**: AMOADD.W atomically loads a data value from the address in rs1, places the value into register rd, then adds the loaded value and the original value in rs2, then stores the result back to the address in rs1.
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**Pseudocode**: x[rd] = AMO32(M[x[rs1]] + x[rs2])
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**Invalid values**: NONE
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**Exception raised**: If the address is not naturally aligned (4-byte boundary), a misaligned address exception will be generated.
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- **AMOAND.W**: Atomic Memory Operation: And Word
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**Format**: amoand.w rd, rs2, (rs1)
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**Description**: AMOAND.W atomically loads a data value from the address in rs1, places the value into register rd, then performs an AND between the loaded value and the original value in rs2, then stores the result back to the address in rs1.
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**Pseudocode**: x[rd] = AMO32(M[x[rs1]] & x[rs2])
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**Invalid values**: NONE
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**Exception raised**: If the address is not naturally aligned (4-byte boundary), a misaligned address exception will be generated.
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- **AMOOR.W**: Atomic Memory Operation: Or Word
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**Format**: amoor.w rd, rs2, (rs1)
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**Description**: AMOOR.W atomically loads a data value from the address in rs1, places the value into register rd, then performs an OR between the loaded value and the original value in rs2, then stores the result back to the address in rs1.
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**Pseudocode**: x[rd] = AMO32(M[x[rs1]] | x[rs2])
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**Invalid values**: NONE
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**Exception raised**: If the address is not naturally aligned (4-byte boundary), a misaligned address exception will be generated.
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- **AMOXOR.W**: Atomic Memory Operation: Xor Word
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**Format**: amoxor.w rd, rs2, (rs1)
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**Description**: AMOXOR.W atomically loads a data value from the address in rs1, places the value into register rd, then performs a XOR between the loaded value and the original value in rs2, then stores the result back to the address in rs1.
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**Pseudocode**: x[rd] = AMO32(M[x[rs1]] ^ x[rs2])
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**Invalid values**: NONE
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**Exception raised**: If the address is not naturally aligned (4-byte boundary), a misaligned address exception will be generated.
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- **AMOSWAP.W**: Atomic Memory Operation: Swap Word
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**Format**: amoswap.w rd, rs2, (rs1)
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**Description**: AMOSWAP.W atomically loads a data value from the address in rs1, places the value into register rd, then performs a SWAP between the loaded value and the original value in rs2, then stores the result back to the address in rs1.
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**Pseudocode**: x[rd] = AMO32(M[x[rs1]] SWAP x[rs2])
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**Invalid values**: NONE
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**Exception raised**: If the address is not naturally aligned (4-byte boundary), a misaligned address exception will be generated.
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- **AMOMIN.W**: Atomic Memory Operation: Minimum Word
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**Format**: amomin.d rd, rs2, (rs1)
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**Description**: AMOMIN.W atomically loads a data value from the address in rs1, places the value into register rd, then choses the minimum between the loaded value and the original value in rs2, then stores the result back to the address in rs1.
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**Pseudocode**: x[rd] = AMO32(M[x[rs1]] MIN x[rs2])
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**Invalid values**: NONE
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**Exception raised**: If the address is not naturally aligned (4-byte boundary), a misaligned address exception will be generated.
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- **AMOMINU.W**: Atomic Memory Operation: Minimum Word, Unsigned
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**Format**: amominu.d rd, rs2, (rs1)
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**Description**: AMOMINU.W atomically loads a data value from the address in rs1, places the value into register rd, then choses the minimum (the values treated as unsigned) between the loaded value and the original value in rs2, then stores the result back to the address in rs1.
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**Pseudocode**: x[rd] = AMO32(M[x[rs1]] MINU x[rs2])
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**Invalid values**: NONE
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**Exception raised**: If the address is not naturally aligned (4-byte boundary), a misaligned address exception will be generated.
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- **AMOMAX.W**: Atomic Memory Operation: Maximum Word, Unsigned
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**Format**: amomax.d rd, rs2, (rs1)
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**Description**: AMOMAX.W atomically loads a data value from the address in rs1, places the value into register rd, then choses the maximum between the loaded value and the original value in rs2, then stores the result back to the address in rs1.
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**Pseudocode**: x[rd] = AMO32(M[x[rs1]] MAX x[rs2])
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**Invalid values**: NONE
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**Exception raised**: If the address is not naturally aligned (4-byte boundary), a misaligned address exception will be generated.
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- **AMOMAXU.W**: Atomic Memory Operation: Maximum Word, Unsigned
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**Format**: amomaxu.d rd, rs2, (rs1)
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**Description**: AMOMAXU.W atomically loads a data value from the address in rs1, places the value into register rd, then choses the maximum (the values treated as unsigned) between the loaded value and the original value in rs2, then stores the result back to the address in rs1.
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**Pseudocode**: x[rd] = AMO32(M[x[rs1]] MAXU x[rs2])
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**Invalid values**: NONE
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**Exception raised**: If the address is not naturally aligned (4-byte boundary), a misaligned address exception will be generated.
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370
docs/01_cva6_user/RISCV_Instructions_RV32C.rst
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370
docs/01_cva6_user/RISCV_Instructions_RV32C.rst
Normal file
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@ -0,0 +1,370 @@
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..
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Copyright (c) 2023 OpenHW Group
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Copyright (c) 2023 Thales
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SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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.. Level 1
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=======
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Level 2
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-------
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Level 3
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~~~~~~~
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Level 4
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^^^^^^^
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.. _cva6_riscv_instructions_RV32C:
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*Applicability of this chapter to configurations:*
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.. csv-table::
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:widths: auto
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:align: left
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:header: "Configuration", "Implementation"
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"CV32A60X", "Implemented extension"
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"CV32E6?X", "Implemented extension"
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**Note**: This chapter is specific to CV32A6 configurations. CV64A6 configurations implement as an option RV64C, that includes a different list of instructions.
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RV32C Compressed Instructions
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-----------------------------
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RVC uses a simple compression scheme that offers shorter 16-bit versions of common 32-bit RISC-V
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instructions when:
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• the immediate or address offset is small;
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• one of the registers is the zero register (x0), the ABI link register (x1), or the ABI stack pointer (x2);
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• the destination register and the first source register are identical;
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• the registers used are the 8 most popular ones.
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The C extension is compatible with all other standard instruction extensions. The C extension
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allows 16-bit instructions to be freely intermixed with 32-bit instructions, with the latter now able
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to start on any 16-bit boundary. With the addition of the C extension, JAL and JALR instructions
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will no longer raise an instruction misaligned exception.
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Integer Computational Instructions
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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- **C.LI**: Compressed Load Immediate
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**Format**: c.li rd, imm[5:0]
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**Description**: loads the sign-extended 6-bit immediate, imm, into register rd.
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**Pseudocode**: x[rd] = sext(imm[5:0])
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**Invalid values**: rd = x0
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**Exception raised**: NONE
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- **C.LUI**: Compressed Load Upper Immediate
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**Format**: c.lui rd, nzimm[17:12]
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**Description**: loads the non-zero 6-bit immediate field into bits 17–12 of the destination register, clears the bottom 12 bits, and sign-extends bit 17 into all higher bits of the destination.
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**Pseudocode**: x[rd] = sext(nzimm[17:12] << 12)
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**Invalid values**: rd = x0 & rd = x2 & nzimm = 0
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**Exception raised**: NONE
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- **C.ADDI**: Compressed Addition Immediate
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**Format**: c.addi rd, nzimm[5:0]
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**Description**: adds the non-zero sign-extended 6-bit immediate to the value in register rd then writes the result to rd.
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**Pseudocode**: x[rd] = x[rd] + sext(nzimm[5:0])
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**Invalid values**: rd = x0 & nzimm = 0
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**Exception raised**: NONE
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- **C.ADDI16SP**: Addition Immediate Scaled by 16, to Stack Pointer
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**Format**: c.addi16sp nzimm[9:4]
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**Description**: adds the non-zero sign-extended 6-bit immediate to the value in the stack pointer (sp=x2), where the immediate is scaled to represent multiples of 16 in the range (-512,496). C.ADDI16SP is used to adjust the stack pointer in procedure prologues and epilogues. C.ADDI16SP shares the opcode with C.LUI, but has a destination field of x2.
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**Pseudocode**: x[2] = x[2] + sext(nzimm[9:4])
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**Invalid values**: rd != x2 & nzimm = 0
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**Exception raised**: NONE
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- **C.ADDI4SPN**: Addition Immediate Scaled by 4, to Stack Pointer
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**Format**: c.addi4spn rd', nzimm[9:2]
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**Description**: adds a zero-extended non-zero immediate, scaled by 4, to the stack pointer, x2, and writes the result to rd'. This instruction is used to generate pointers to stack-allocated variables.
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**Pseudocode**: x[8 + rd'] = x[2] + zext(nzimm[9:2])
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**Invalid values**: nzimm = 0
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**Exception raised**: NONE
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- **C.SLLI**: Compressed Shift Left Logic Immediate
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**Format**: c.slli rd, uimm[5:0]
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**Description**: performs a logical left shift (zeros are shifted into the lower bits).
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**Pseudocode**: x[rd] = x[rd] << uimm[5:0]
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**Invalid values**: rd = x0 & uimm[5] = 0
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**Exception raised**: NONE
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- **C.SRLI**: Compressed Shift Right Logic Immediate
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**Format**: c.srli rd', uimm[5:0]
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**Description**: performs a logical right shift (zeros are shifted into the upper bits).
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**Pseudocode**: x[8 + rd'] = x[8 + rd'] >> uimm[5:0]
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**Invalid values**: uimm[5] = 0
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**Exception raised**: NONE
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- **C.SRAI**: Compressed Shift Right Arithmetic Immediate
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**Format**: c.srai rd', uimm[5:0]
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**Description**: performs an arithmetic right shift (sign bits are shifted into the upper bits).
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**Pseudocode**: x[8 + rd'] = x[8 + rd'] >>s uimm[5:0]
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**Invalid values**: uimm[5] = 0
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**Exception raised**: NONE
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- **C.ANDI**: Compressed AND Immediate
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**Format**: c.andi rd', imm[5:0]
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**Description**: computes the bitwise AND of the value in register rd', and the sign-extended 6-bit immediate, then writes the result to rd'.
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**Pseudocode**: x[8 + rd'] = x[8 + rd'] & sext(imm[5:0])
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**Invalid values**: NONE
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**Exception raised**: NONE
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- **C.ADD**: Compressed Addition
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**Format**: c.add rd, rs2
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**Description**: adds the values in registers rd and rs2 and writes the result to register rd.
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**Pseudocode**: x[rd] = x[rd] + x[rs2]
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**Invalid values**: rd = x0 & rs2 = x0
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**Exception raised**: NONE
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- **C.MV**: Move
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**Format**: c.mv rd, rs2
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**Description**: copies the value in register rs2 into register rd.
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**Pseudocode**: x[rd] = x[rs2]
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**Invalid values**: rd = x0 & rs2 = x0
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**Exception raised**: NONE
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- **C.AND**: Compressed AND
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**Format**: c.and rd', rs2'
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**Description**: computes the bitwise AND of of the value in register rd', and register rs2', then writes the result to rd'.
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**Pseudocode**: x[8 + rd'] = x[8 + rd'] & x[8 + rs2']
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**Invalid values**: NONE
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**Exception raised**: NONE
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- **C.OR**: Compressed OR
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**Format**: c.or rd', rs2'
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**Description**: computes the bitwise OR of of the value in register rd', and register rs2', then writes the result to rd'.
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**Pseudocode**: x[8 + rd'] = x[8 + rd'] | x[8 + rs2']
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**Invalid values**: NONE
|
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**Exception raised**: NONE
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- **C.XOR**: Compressed XOR
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**Format**: c.and rd', rs2'
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**Description**: computes the bitwise XOR of of the value in register rd', and register rs2', then writes the result to rd'.
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**Pseudocode**: x[8 + rd'] = x[8 + rd'] ^ x[8 + rs2']
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**Invalid values**: NONE
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**Exception raised**: NONE
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- **C.SUB**: Compressed Subtraction
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**Format**: c.sub rd', rs2'
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**Description**: subtracts the value in registers rs2' from value in rd' and writes the result to register rd'.
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**Pseudocode**: x[8 + rd'] = x[8 + rd'] - x[8 + rs2']
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**Invalid values**: NONE
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**Exception raised**: NONE
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- **C.EBREAK**: Compressed Ebreak
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**Format**: c.ebreak
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**Description**: cause control to be transferred back to the debugging environment.
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|
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**Pseudocode**: RaiseException(Breakpoint)
|
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**Invalid values**: NONE
|
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**Exception raised**: Raise a Breakpoint exception.
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Control Transfer Instructions
|
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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- **C.J**: Compressed Jump
|
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**Format**: c.j imm[11:1]
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**Description**: performs an unconditional control transfer. The offset is sign-extended and added to the pc to form the jump target address.
|
||||
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**Pseudocode**: pc += sext(imm[11:1])
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**Invalid values**: NONE
|
||||
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||||
**Exception raised**: jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception.
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||||
|
||||
- **C.JAL**: Compressed Jump and Link
|
||||
|
||||
**Format**: c.jal imm[11:1]
|
||||
|
||||
**Description**: performs the same operation as C.J, but additionally writes the address of the instruction following the jump (pc+2) to the link register, x1.
|
||||
|
||||
**Pseudocode**: x[1] = pc+2; pc += sext(imm[11:1])
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception.
|
||||
|
||||
- **C.JR**: Compressed Jump Register
|
||||
|
||||
**Format**: c.jr rs1
|
||||
|
||||
**Description**: performs an unconditional control transfer to the address in register rs1.
|
||||
|
||||
**Pseudocode**: pc = x[rs1]
|
||||
|
||||
**Invalid values**: rs1 = x0
|
||||
|
||||
**Exception raised**: jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception.
|
||||
|
||||
- **C.JALR**: Compressed Jump and Link Register
|
||||
|
||||
**Format**: c.jalr rs1
|
||||
|
||||
**Description**: performs the same operation as C.JR, but additionally writes the address of the instruction following the jump (pc+2) to the link register, x1.
|
||||
|
||||
**Pseudocode**: t = pc+2; pc = x[rs1]; x[1] = t
|
||||
|
||||
**Invalid values**: rs1 = x0
|
||||
|
||||
**Exception raised**: jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception.
|
||||
|
||||
- **C.BEQZ**: Branch if Equal Zero
|
||||
|
||||
**Format**: c.beqz rs1', imm[8:1]
|
||||
|
||||
**Description**: performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. C.BEQZ takes the branch if the value in register rs1' is zero.
|
||||
|
||||
**Pseudocode**: if (x[8+rs1'] == 0) pc += sext(imm[8:1])
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions.
|
||||
|
||||
- **C.BNEZ**: Branch if Not Equal Zero
|
||||
|
||||
**Format**: c.bnez rs1', imm[8:1]
|
||||
|
||||
**Description**: performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. C.BEQZ takes the branch if the value in register rs1' isn't zero.
|
||||
|
||||
**Pseudocode**: if (x[8+rs1'] != 0) pc += sext(imm[8:1])
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions.
|
||||
|
||||
Load and Store Instructions
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
- **C.LWSP**: Load Word Stack-Pointer
|
||||
|
||||
**Format**: c.lwsp rd, uimm(x2)
|
||||
|
||||
**Description**: loads a 32-bit value from memory into register rd. It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2.
|
||||
|
||||
**Pseudocode**: x[rd] = M[x[2] + zext(uimm[7:2])][31:0]
|
||||
|
||||
**Invalid values**: rd = x0
|
||||
|
||||
**Exception raised**: loads with a destination of x0 must still raise any exceptions, also an exception if the memory address isn't aligned (4-byte boundary).
|
||||
|
||||
- **C.SWSP**: Store Word Stack-Pointer
|
||||
|
||||
**Format**: c.swsp rd, uimm(x2)
|
||||
|
||||
**Description**: stores a 32-bit value in register rs2 to memory. It computes an effective address by adding the zero-extended offset, scaled by 4, to the stack pointer, x2.
|
||||
|
||||
**Pseudocode**: M[x[2] + zext(uimm[7:2])][31:0] = x[rs2]
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: an exception raised if the memory address isn't aligned (4-byte boundary).
|
||||
|
||||
- **C.LW**: Compressed Load Word
|
||||
|
||||
**Format**: c.lw rd', uimm(rs1')
|
||||
|
||||
**Description**: loads a 32-bit value from memory into register rd'. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1'.
|
||||
|
||||
**Pseudocode**: x[8+rd'] = M[x[8+rs1'] + zext(uimm[6:2])][31:0])
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: an exception raised if the memory address isn't aligned (4-byte boundary).
|
||||
|
||||
- **C.SW**: Compressed Store Word
|
||||
|
||||
**Format**: c.sw rs2', uimm(rs1')
|
||||
|
||||
**Description**: stores a 32-bit value from memory into register rd'. It computes an effective address by adding the zero-extended offset, scaled by 4, to the base address in register rs1'.
|
||||
|
||||
**Pseudocode**: M[x[8+rs1'] + zext(uimm[6:2])][31:0] = x[8+rs2']
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: an exception raised if the memory address isn't aligned (4-byte boundary).
|
||||
|
||||
542
docs/01_cva6_user/RISCV_Instructions_RV32I.rst
Normal file
542
docs/01_cva6_user/RISCV_Instructions_RV32I.rst
Normal file
|
|
@ -0,0 +1,542 @@
|
|||
..
|
||||
Copyright (c) 2023 OpenHW Group
|
||||
Copyright (c) 2023 Thales
|
||||
|
||||
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
.. Level 1
|
||||
=======
|
||||
|
||||
Level 2
|
||||
-------
|
||||
|
||||
Level 3
|
||||
~~~~~~~
|
||||
|
||||
Level 4
|
||||
^^^^^^^
|
||||
|
||||
.. _cva6_riscv_instructions_RV32I:
|
||||
|
||||
*Applicability of this chapter to configurations:*
|
||||
|
||||
This chapter is applicable to all CV32A6 configurations.
|
||||
|
||||
.. csv-table::
|
||||
:widths: auto
|
||||
:align: left
|
||||
:header: "Configuration", "Implementation"
|
||||
|
||||
"CV32A60X", "Implemented extension"
|
||||
"CV32E6?X", "Implemented extension"
|
||||
|
||||
**Note**: CV64A6 implements RV64I that includes additional instructions.
|
||||
|
||||
|
||||
RV32I Base Integer Instruction Set
|
||||
-----------------------------------
|
||||
|
||||
This section describes the RV32I base integer instruction set.
|
||||
|
||||
Integer Register-Immediate Instructions
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
- **ADDI**: Add Immediate
|
||||
|
||||
**Format**: addi rd, rs1, imm[11:0]
|
||||
|
||||
**Description**: add sign-extended 12-bit immediate to register rs1, and store the result in register rd.
|
||||
|
||||
**Pseudocode**: x[rd] = x[rs1] + sext(imm[11:0])
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
- **ANDI**: AND Immediate
|
||||
|
||||
**Format**: andi rd, rs1, imm[11:0]
|
||||
|
||||
**Description**: perform bitwise AND on register rs1 and the sign-extended 12-bit immediate and place the result in rd.
|
||||
|
||||
**Pseudocode**: x[rd] = x[rs1] & sext(imm[11:0])
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
- **ORI**: OR Immediate
|
||||
|
||||
**Format**: ori rd, rs1, imm[11:0]
|
||||
|
||||
**Description**: perform bitwise OR on register rs1 and the sign-extended 12-bit immediate and place the result in rd.
|
||||
|
||||
**Pseudocode**: x[rd] = x[rs1] | sext(imm[11:0])
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
- **XORI**: XOR Immediate
|
||||
|
||||
**Format**: xori rd, rs1, imm[11:0]
|
||||
|
||||
**Description**: perform bitwise XOR on register rs1 and the sign-extended 12-bit immediate and place the result in rd.
|
||||
|
||||
**Pseudocode**: x[rd] = x[rs1] ^ sext(imm[11:0])
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
- **SLTI**: Set Less Then Immediate
|
||||
|
||||
**Format**: slti rd, rs1, imm[11:0]
|
||||
|
||||
**Description**: set register rd to 1 if register rs1 is less than the sign extended immediate when both are treated as signed numbers, else 0 is written to rd.
|
||||
|
||||
**Pseudocode**: if (x[rs1] < sext(imm[11:0]) x[rd] = 1 else x[rd] = 0
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
- **SLTIU**: Set Less Then Immediate Unsigned
|
||||
|
||||
**Format**: sltiu rd, rs1, imm[11:0]
|
||||
|
||||
**Description**: set register rd to 1 if register rs1 is less than the sign extended immediate when both are treated as unsigned numbers, else 0 is written to rd.
|
||||
|
||||
**Pseudocode**: if (x[rs1] <u sext(imm[11:0]) x[rd] = 1 else x[rd] = 0
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
- **SLLI**: Shift Left Logic Immediate
|
||||
|
||||
**Format**: slli rd, rs1, imm[4:0]
|
||||
|
||||
**Description**: logical left shift (zeros are shifted into the lower bits).
|
||||
|
||||
**Pseudocode**: x[rd] = x[rs1] << imm[4:0]
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
- **SRLI**: Shift Right Logic Immediate
|
||||
|
||||
**Format**: srli rd, rs1, imm[4:0]
|
||||
|
||||
**Description**: logical right shift (zeros are shifted into the upper bits).
|
||||
|
||||
**Pseudocode**: x[rd] = x[rs1] >> imm[4:0]
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
- **SRAI**: Shift Right Arithmetic Immediate
|
||||
|
||||
**Format**: srai rd, rs1, imm[4:0]
|
||||
|
||||
**Description**: arithmetic right shift (the original sign bit is copied into the vacated upper bits).
|
||||
|
||||
**Pseudocode**: x[rd] = x[rs1] >>s imm[4:0]
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
- **LUI**: Load Upper Immediate
|
||||
|
||||
**Format**: lui rd, imm[19:0]
|
||||
|
||||
**Description**: place the immediate value in the top 20 bits of the destination register rd, filling in the lowest 12 bits with zeros.
|
||||
|
||||
**Pseudocode**: x[rd] = sext(imm[31:12] << 12)
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
- **AUIPC**: Add Upper Immediate to PC
|
||||
|
||||
**Format**: auipc rd, imm[19:0]
|
||||
|
||||
**Description**: form a 32-bit offset from the 20-bit immediate, filling in the lowest 12 bits with zeros, adds this offset to the pc, then place the result in register rd.
|
||||
|
||||
**Pseudocode**: x[rd] = pc + sext(immediate[31:12] << 12)
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
Integer Register-Register Instructions
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
- **ADD**: Addition
|
||||
|
||||
**Format**: add rd, rs1, rs2
|
||||
|
||||
**Description**: add rs2 to register rs1, and store the result in register rd.
|
||||
|
||||
**Pseudocode**: x[rd] = x[rs1] + x[rs2]
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
- **SUB**: Subtraction
|
||||
|
||||
**Format**: sub rd, rs1, rs2
|
||||
|
||||
**Description**: subtract rs2 from register rs1, and store the result in register rd.
|
||||
|
||||
**Pseudocode**: x[rd] = x[rs1] - x[rs2]
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
- **AND**: AND logical operator
|
||||
|
||||
**Format**: and rd, rs1, rs2
|
||||
|
||||
**Description**: perform bitwise AND on register rs1 and rs2 and place the result in rd.
|
||||
|
||||
**Pseudocode**: x[rd] = x[rs1] & x[rs2]
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
- **OR**: OR logical operator
|
||||
|
||||
**Format**: or rd, rs1, rs2
|
||||
|
||||
**Description**: perform bitwise OR on register rs1 and rs2 and place the result in rd.
|
||||
|
||||
**Pseudocode**: x[rd] = x[rs1] | x[rs2]
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
- **XOR**: XOR logical operator
|
||||
|
||||
**Format**: xor rd, rs1, rs2
|
||||
|
||||
**Description**: perform bitwise XOR on register rs1 and rs2 and place the result in rd.
|
||||
|
||||
**Pseudocode**: x[rd] = x[rs1] ^ x[rs2]
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
- **SLT**: Set Less Then
|
||||
|
||||
**Format**: slt rd, rs1, rs2
|
||||
|
||||
**Description**: set register rd to 1 if register rs1 is less than rs2 when both are treated as signed numbers, else 0 is written to rd.
|
||||
|
||||
**Pseudocode**: if (x[rs1] < x[rs2]) x[rd] = 1 else x[rd] = 0
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
- **SLTU**: Set Less Then Unsigned
|
||||
|
||||
**Format**: sltu rd, rs1, rs2
|
||||
|
||||
**Description**: set register rd to 1 if register rs1 is less than rs2 when both are treated as unsigned numbers, else 0 is written to rd.
|
||||
|
||||
**Pseudocode**: if (x[rs1] <u x[rs2]) x[rd] = 1 else x[rd] = 0
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
- **SLL**: Shift Left Logic
|
||||
|
||||
**Format**: sll rd, rs1, rs2
|
||||
|
||||
**Description**: logical left shift (zeros are shifted into the lower bits).
|
||||
|
||||
**Pseudocode**: x[rd] = x[rs1] << x[rs2]
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
- **SRL**: Shift Right Logic
|
||||
|
||||
**Format**: srl rd, rs1, rs2
|
||||
|
||||
**Description**: logical right shift (zeros are shifted into the upper bits).
|
||||
|
||||
**Pseudocode**: x[rd] = x[rs1] >> x[rs2]
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
- **SRA**: Shift Right Arithmetic
|
||||
|
||||
**Format**: sra rd, rs1, rs2
|
||||
|
||||
**Description**: arithmetic right shift (the original sign bit is copied into the vacated upper bits).
|
||||
|
||||
**Pseudocode**: x[rd] = x[rs1] >>s x[rs2]
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
Control Transfer Instructions
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
**Unconditional Jumps**
|
||||
|
||||
- **JAL**: Jump and Link
|
||||
|
||||
**Format**: jal rd, imm[20:1]
|
||||
|
||||
**Description**: offset is sign-extended and added to the pc to form the jump target address (pc is calculated using signed arithmetic), then setting the least-significant bit of the result to zero, and store the address of instruction following the jump (pc+4) into register rd.
|
||||
|
||||
**Pseudocode**: x[rd] = pc+4; pc += sext(imm[20:1])
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception.
|
||||
|
||||
- **JALR**: Jump and Link Register
|
||||
|
||||
**Format**: jalr rd, rs1, imm[11:0]
|
||||
|
||||
**Description**: target address is obtained by adding the 12-bit signed immediate to the register rs1 (pc is calculated using signed arithmetic), then setting the least-significant bit of the result to zero, and store the address of instruction following the jump (pc+4) into register rd.
|
||||
|
||||
**Pseudocode**: t = pc+4; pc = (x[rs1]+sext(imm[11:0]))&∼1 ; x[rd] = t
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: jumps to an unaligned address (4-byte or 2-byte boundary) will usually raise an exception.
|
||||
|
||||
**Conditional Branches**
|
||||
|
||||
- **BEQ**: Branch Equal
|
||||
|
||||
**Format**: beq rs1, rs2, imm[12:1]
|
||||
|
||||
**Description**: takes the branch (pc is calculated using signed arithmetic) if registers rs1 and rs2 are equal.
|
||||
|
||||
**Pseudocode**: if (x[rs1] == x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions.
|
||||
|
||||
- **BNE**: Branch Not Equal
|
||||
|
||||
**Format**: bne rs1, rs2, imm[12:1]
|
||||
|
||||
**Description**: takes the branch (pc is calculated using signed arithmetic) if registers rs1 and rs2 are not equal.
|
||||
|
||||
**Pseudocode**: if (x[rs1] != x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions.
|
||||
|
||||
- **BLT**: Branch Less Than
|
||||
|
||||
**Format**: blt rs1, rs2, imm[12:1]
|
||||
|
||||
**Description**: takes the branch (pc is calculated using signed arithmetic) if registers rs1 less than rs2 (using signed comparison).
|
||||
|
||||
**Pseudocode**: if (x[rs1] < x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions.
|
||||
|
||||
- **BLTU**: Branch Less Than Unsigned
|
||||
|
||||
**Format**: bltu rs1, rs2, imm[12:1]
|
||||
|
||||
**Description**: takes the branch (pc is calculated using signed arithmetic) if registers rs1 less than rs2 (using unsigned comparison).
|
||||
|
||||
**Pseudocode**: if (x[rs1] <u x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions.
|
||||
|
||||
- **BGE**: Branch Greater or Equal
|
||||
|
||||
**Format**: bge rs1, rs2, imm[12:1]
|
||||
|
||||
**Description**: takes the branch (pc is calculated using signed arithmetic) if registers rs1 is greater than or equal rs2 (using signed comparison).
|
||||
|
||||
**Pseudocode**: if (x[rs1] >= x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions.
|
||||
|
||||
- **BGEU**: Branch Greater or Equal Unsigned
|
||||
|
||||
**Format**: bgeu rs1, rs2, imm[12:1]
|
||||
|
||||
**Description**: takes the branch (pc is calculated using signed arithmetic) if registers rs1 is greater than or equal rs2 (using unsigned comparison).
|
||||
|
||||
**Pseudocode**: if (x[rs1] >=u x[rs2]) pc += sext({imm[12:1], 1’b0}) else pc += 4
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: no instruction fetch misaligned exception is generated for a conditional branch that is not taken. An Instruction address misaligned exception is raised if the target address is not aligned on 4-byte or 2-byte boundary, because the core supports compressed instructions.
|
||||
|
||||
Load and Store Instructions
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
- **LB**: Load Byte
|
||||
|
||||
**Format**: lb rd, imm(rs1)
|
||||
|
||||
**Description**: loads a 8-bit value from memory, then sign-extends to 32-bit before storing in rd (rd is calculated using signed arithmetic), the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset.
|
||||
|
||||
**Pseudocode**: x[rd] = sext(M[x[rs1] + sext(imm[11:0])][7:0])
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: loads with a destination of x0 must still raise any exceptions and action any other side effects even though the load value is discarded.
|
||||
|
||||
- **LH**: Load Halfword
|
||||
|
||||
**Format**: lh rd, imm(rs1)
|
||||
|
||||
**Description**: loads a 16-bit value from memory, then sign-extends to 32-bit before storing in rd (rd is calculated using signed arithmetic), the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset.
|
||||
|
||||
**Pseudocode**: x[rd] = sext(M[x[rs1] + sext(imm[11:0])][15:0])
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: loads with a destination of x0 must still raise any exceptions and action any other side effects even though the load value is discarded, also an exception is raised if the memory address isn't aligned (2-byte boundary).
|
||||
|
||||
- **LW**: Load Word
|
||||
|
||||
**Format**: lw rd, imm(rs1)
|
||||
|
||||
**Description**: loads a 32-bit value from memory, then storing in rd (rd is calculated using signed arithmetic). The effective address is obtained by adding register rs1 to the sign-extended 12-bit offset.
|
||||
|
||||
**Pseudocode**: x[rd] = sext(M[x[rs1] + sext(imm[11:0])][31:0])
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: loads with a destination of x0 must still raise any exceptions and action any other side effects even though the load value is discarded, also an exception is raised if the memory address isn't aligned (4-byte boundary).
|
||||
|
||||
- **LBU**: Load Byte Unsigned
|
||||
|
||||
**Format**: lbu rd, imm(rs1)
|
||||
|
||||
**Description**: loads a 8-bit value from memory, then zero-extends to 32-bit before storing in rd (rd is calculated using unsigned arithmetic), the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset.
|
||||
|
||||
**Pseudocode**: x[rd] = zext(M[x[rs1] + sext(imm[11:0])][7:0])
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: loads with a destination of x0 must still raise any exceptions and action any other side effects even though the load value is discarded.
|
||||
|
||||
- **LHU**: Load Halfword Unsigned
|
||||
|
||||
**Format**: lhu rd, imm(rs1)
|
||||
|
||||
**Description**: loads a 16-bit value from memory, then zero-extends to 32-bit before storing in rd (rd is calculated using unsigned arithmetic), the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset.
|
||||
|
||||
**Pseudocode**: x[rd] = zext(M[x[rs1] + sext(imm[11:0])][15:0])
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: loads with a destination of x0 must still raise any exceptions and action any other side effects even though the load value is discarded, also an exception is raised if the memory address isn't aligned (2-byte boundary).
|
||||
|
||||
- **SB**: Store Byte
|
||||
|
||||
**Format**: sb rs2, imm(rs1)
|
||||
|
||||
**Description**: stores a 8-bit value from the low bits of register rs2 to memory, the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset.
|
||||
|
||||
**Pseudocode**: M[x[rs1] + sext(imm[11:0])][7:0] = x[rs2][7:0]
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
- **SH**: Store Halfword
|
||||
|
||||
**Format**: sh rs2, imm(rs1)
|
||||
|
||||
**Description**: stores a 16-bit value from the low bits of register rs2 to memory, the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset.
|
||||
|
||||
**Pseudocode**: M[x[rs1] + sext(imm[11:0])][15:0] = x[rs2][15:0]
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: an exception is raised if the memory address isn't aligned (2-byte boundary).
|
||||
|
||||
- **SW**: Store Word
|
||||
|
||||
**Format**: sw rs2, imm(rs1)
|
||||
|
||||
**Description**: stores a 32-bit value from register rs2 to memory, the effective address is obtained by adding register rs1 to the sign-extended 12-bit offset.
|
||||
|
||||
**Pseudocode**: M[x[rs1] + sext(imm[11:0])][31:0] = x[rs2][31:0]
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: an exception is raised if the memory address isn't aligned (4-byte boundary).
|
||||
|
||||
Memory Ordering
|
||||
^^^^^^^^^^^^^^^^^^
|
||||
|
||||
- **FENCE**: Fence Instruction
|
||||
|
||||
**Format**: fence pre, succ
|
||||
|
||||
**Description**: order device I/O and memory accesses as viewed by other RISC-V harts and external devices or coprocessors. Any combination of device input (I), device output (O), memory reads (R), and memory writes (W) may be ordered with respect to any combination of the same. Informally, no other RISC-V hart or external device can observe any operation in the successor set following a FENCE before any operation in the predecessor set preceding the FENCE, as the core support 1 hart, the fence instruction has no effect so we can considerate it as a nop instruction.
|
||||
|
||||
**Pseudocode**: No operation (nop)
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
Environment Call and Breakpoints
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
- **ECALL**: Environment Call
|
||||
|
||||
**Format**: ecall
|
||||
|
||||
**Description**: make a request to the supporting execution environment, which is usually an operating system. The ABI for the system will define how parameters for the environment request are passed, but usually these will be in defined locations in the integer register file.
|
||||
|
||||
**Pseudocode**: RaiseException(EnvironmentCall)
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: Raise an Environment Call exception.
|
||||
|
||||
- **EBREAK**:Environment Break
|
||||
|
||||
**Format**: ebreak
|
||||
|
||||
**Description**: cause control to be transferred back to a debugging environment.
|
||||
|
||||
**Pseudocode**: RaiseException(Breakpoint)
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: Raise a Breakpoint exception.
|
||||
|
||||
143
docs/01_cva6_user/RISCV_Instructions_RV32M.rst
Normal file
143
docs/01_cva6_user/RISCV_Instructions_RV32M.rst
Normal file
|
|
@ -0,0 +1,143 @@
|
|||
..
|
||||
Copyright (c) 2023 OpenHW Group
|
||||
Copyright (c) 2023 Thales
|
||||
|
||||
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
.. Level 1
|
||||
=======
|
||||
|
||||
Level 2
|
||||
-------
|
||||
|
||||
Level 3
|
||||
~~~~~~~
|
||||
|
||||
Level 4
|
||||
^^^^^^^
|
||||
|
||||
.. _cva6_riscv_instructions_RV32M:
|
||||
|
||||
*Applicability of this chapter to configurations:*
|
||||
|
||||
This chapter is applicable to all CV32A6 configurations.
|
||||
|
||||
.. csv-table::
|
||||
:widths: auto
|
||||
:align: left
|
||||
:header: "Configuration", "Implementation"
|
||||
|
||||
"CV32A60X", "Implemented extension"
|
||||
"CV32E6?X", "Implemented extension"
|
||||
|
||||
**Note**: CV64A6 implements RV64M that includes additional instructions.
|
||||
|
||||
|
||||
RV32M Multiplication and Division Instructions
|
||||
------------------------------------------------------
|
||||
|
||||
This chapter describes the standard integer multiplication and division instruction extension, which
|
||||
is named “M” and contains instructions that multiply or divide values held in two integer registers.
|
||||
|
||||
Multiplication Operations
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
- **MUL**: Multiplication
|
||||
|
||||
**Format**: mul rd, rs1, rs2
|
||||
|
||||
**Description**: performs a 32-bit × 32-bit multiplication and places the lower 32 bits in the destination register (Both rs1 and rs2 treated as signed numbers).
|
||||
|
||||
**Pseudocode**: x[rd] = x[rs1] * x[rs2]
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
- **MULH**: Multiplication Higher
|
||||
|
||||
**Format**: mulh rd, rs1, rs2
|
||||
|
||||
**Description**: performs a 32-bit × 32-bit multiplication and places the upper 32 bits in the destination register of the 64-bit product (Both rs1 and rs2 treated as signed numbers).
|
||||
|
||||
**Pseudocode**: x[rd] = (x[rs1] s*s x[rs2]) >>s 32
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
- **MULHU**: Multiplication Higher Unsigned
|
||||
|
||||
**Format**: mulhu rd, rs1, rs2
|
||||
|
||||
**Description**: performs a 32-bit × 32-bit multiplication and places the upper 32 bits in the destination register of the 64-bit product (Both rs1 and rs2 treated as unsigned numbers).
|
||||
|
||||
**Pseudocode**: x[rd] = (x[rs1] u*u x[rs2]) >>u 32
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
- **MULHSU**: Multiplication Higher Signed Unsigned
|
||||
|
||||
**Format**: mulhsu rd, rs1, rs2
|
||||
|
||||
**Description**: performs a 32-bit × 32-bit multiplication and places the upper 32 bits in the destination register of the 64-bit product (rs1 treated as signed number, rs2 treated as unsigned number).
|
||||
|
||||
**Pseudocode**: x[rd] = (x[rs1] s*u x[rs2]) >>s 32
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
Division Operations
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
- **DIV**: Division
|
||||
|
||||
**Format**: div rd, rs1, rs2
|
||||
|
||||
**Description**: perform signed integer division of 32 bits by 32 bits (rounding towards zero).
|
||||
|
||||
**Pseudocode**: x[rd] = x[rs1] /s x[rs2]
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
- **DIVU**: Division Unsigned
|
||||
|
||||
**Format**: divu rd, rs1, rs2
|
||||
|
||||
**Description**: perform unsigned integer division of 32 bits by 32 bits (rounding towards zero).
|
||||
|
||||
**Pseudocode**: x[rd] = x[rs1] /u x[rs2]
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
- **REM**: Remain
|
||||
|
||||
**Format**: rem rd, rs1, rs2
|
||||
|
||||
**Description**: provide the remainder of the corresponding division operation DIV (the sign of rd equals the sign of rs1).
|
||||
|
||||
**Pseudocode**: x[rd] = x[rs1] %s x[rs2]
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
- **REMU**: Remain Unsigned
|
||||
|
||||
**Format**: rem rd, rs1, rs2
|
||||
|
||||
**Description**: provide the remainder of the corresponding division operation DIVU.
|
||||
|
||||
**Pseudocode**: x[rd] = x[rs1] %u x[rs2]
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
171
docs/01_cva6_user/RISCV_Instructions_RV32ZCb.rst
Normal file
171
docs/01_cva6_user/RISCV_Instructions_RV32ZCb.rst
Normal file
|
|
@ -0,0 +1,171 @@
|
|||
..
|
||||
Copyright (c) 2023 OpenHW Group
|
||||
Copyright (c) 2023 Thales
|
||||
|
||||
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
.. Level 1
|
||||
=======
|
||||
|
||||
Level 2
|
||||
-------
|
||||
|
||||
Level 3
|
||||
~~~~~~~
|
||||
|
||||
Level 4
|
||||
^^^^^^^
|
||||
|
||||
.. _cva6_riscv_instructions_RV32Zcb:
|
||||
|
||||
*Applicability of this chapter to configurations:*
|
||||
|
||||
.. csv-table::
|
||||
:widths: auto
|
||||
:align: left
|
||||
:header: "Configuration", "Implementation"
|
||||
|
||||
"CV32A60X", "Implemented extension"
|
||||
"CV32E6?X", "Implemented extension"
|
||||
|
||||
**Note**: This chapter is specific to CV32A6 configurations. CV64A6 configurations implement as an option RV64Zcb, that includes one additional instruction.
|
||||
|
||||
|
||||
RV32Zcb Code Size Reduction Instructions
|
||||
-----------------------------------------
|
||||
|
||||
Zcb belongs to group of extensions called RISC-V Code Size Reduction Extension (Zc*). Zc* has become the superset of Standard C extension adding more 16-bit instructions to the ISA. Zcb includes 16-bit version of additional Integer (I), Multiply (M) and Bit-Manipulation (Zbb) Instructions.
|
||||
All the Zcb instructions require at least standard C extension support as pre-requisite, along with M and Zbb extensions for 16-bit version of the respective instructions.
|
||||
|
||||
- **C.ZEXT.B**: Compressed Zero Extend Byte
|
||||
|
||||
**Format**: c.zext.b rd'
|
||||
|
||||
**Description**: This instruction takes a single source/destination operand. It zero-extends the least-significant byte of the operand by inserting zeros into all of the bits more significant than 7.
|
||||
|
||||
**Pseudocode**: x[8 + rd'] = zext(x[8 + rd'][7:0])
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
- **C.SEXT.B**: Compressed Sign Extend Byte
|
||||
|
||||
**Format**: c.sext.b rd'
|
||||
|
||||
**Description**: This instruction takes a single source/destination operand. It sign-extends the least-significant byte in the operand by copying the most-significant bit in the byte (i.e., bit 7) to all of the more-significant bits. It also requires Bit-Manipulation (Zbb) extension support.
|
||||
|
||||
**Pseudocode**: x[8 + rd'] = sext(x[8 + rd'][7:0])
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
- **C.ZEXT.H**: Compressed Zero Extend Halfword
|
||||
|
||||
**Format**: c.zext.h rd'
|
||||
|
||||
**Description**: This instruction takes a single source/destination operand. It zero-extends the least-significant halfword of the operand by inserting zeros into all of the bits more significant than 15. It also requires Bit-Manipulation (Zbb) extension support.
|
||||
|
||||
**Pseudocode**: x[8 + rd'] = zext(x[8 + rd'][15:0])
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
- **C.SEXT.H**: Compressed Sign Extend Halfword
|
||||
|
||||
**Format**: c.sext.h rd'
|
||||
|
||||
**Description**: This instruction takes a single source/destination operand. It sign-extends the least-significant halfword in the operand by copying the most-significant bit in the halfword (i.e., bit 15) to all of the more-significant bits. It also requires Bit-Manipulation (Zbb) extension support.
|
||||
|
||||
**Pseudocode**: x[8 + rd'] = sext(x[8 + rd'][15:0])
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
- **C.NOT**: Compressed Bitwise NOT
|
||||
|
||||
**Format**: c.not rd'
|
||||
|
||||
**Description**: This instruction takes the one’s complement of rd'/rs1' and writes the result to the same register.
|
||||
|
||||
**Pseudocode**: x[8 + rd'] = x[8 + rd'] ^ -1
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
- **C.MUL**: Compressed Multiply
|
||||
|
||||
**Format**: c.mul rd', rs2'
|
||||
|
||||
**Description**: performs a 32-bit × 32-bit multiplication and places the lower 32 bits in the destination register (Both rd' and rs2' treated as signed numbers). It also requires M extension support.
|
||||
|
||||
**Pseudocode**: x[8 + rd'] = (x[8 + rd'] * x[8 + rs2'])[31:0]
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
- **C.LHU**: Compressed Load Halfword Unsigned
|
||||
|
||||
**Format**: c.lhu rd', uimm(rs1')
|
||||
|
||||
**Description**: This instruction loads a halfword from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting halfword is zero extended and is written to rd'.
|
||||
|
||||
**Pseudocode**: x[8+rd'] = zext(M[x[8+rs1'] + zext(uimm[1])][15:0])
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: an exception raised if the memory address isn't aligned (2-byte boundary).
|
||||
|
||||
- **C.LH**: Compressed Load Halfword
|
||||
|
||||
**Format**: c.lh rd', uimm(rs1')
|
||||
|
||||
**Description**: This instruction loads a halfword from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting halfword is sign extended and is written to rd'.
|
||||
|
||||
**Pseudocode**: x[8+rd'] = sext(M[x[8+rs1'] + zext(uimm[1])][15:0])
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: an exception raised if the memory address isn't aligned (2-byte boundary).
|
||||
|
||||
- **C.LBU**: Compressed Load Byte Unsigned
|
||||
|
||||
**Format**: c.lbu rd', uimm(rs1')
|
||||
|
||||
**Description**: This instruction loads a byte from the memory address formed by adding rs1' to the zero extended immediate uimm. The resulting byte is zero extended and is written to rd'.
|
||||
|
||||
**Pseudocode**: x[8+rd'] = zext(M[x[8+rs1'] + zext(uimm[1:0])][7:0])
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
- **C.SH**: Compressed Store Halfword
|
||||
|
||||
**Format**: c.sh rs2', uimm(rs1')
|
||||
|
||||
**Description**: This instruction stores the least significant halfword of rs2' to the memory address formed by adding rs1' to the zero extended immediate uimm.
|
||||
|
||||
**Pseudocode**: M[x[8+rs1'] + zext(uimm[1])][15:0] = x[8+rs2']
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: an exception raised if the memory address isn't aligned (2-byte boundary).
|
||||
|
||||
- **C.SB**: Compressed Store Byte
|
||||
|
||||
**Format**: c.sb rs2', uimm(rs1')
|
||||
|
||||
**Description**: This instruction stores the least significant byte of rs2' to the memory address formed by adding rs1' to the zero extended immediate uimm.
|
||||
|
||||
**Pseudocode**: M[x[8+rs1'] + zext(uimm[1:0])][7:0] = x[8+rs2']
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
62
docs/01_cva6_user/RISCV_Instructions_RVZicond.rst
Normal file
62
docs/01_cva6_user/RISCV_Instructions_RVZicond.rst
Normal file
|
|
@ -0,0 +1,62 @@
|
|||
..
|
||||
Copyright (c) 2023 OpenHW Group
|
||||
Copyright (c) 2023 Thales
|
||||
|
||||
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
.. Level 1
|
||||
=======
|
||||
|
||||
Level 2
|
||||
-------
|
||||
|
||||
Level 3
|
||||
~~~~~~~
|
||||
|
||||
Level 4
|
||||
^^^^^^^
|
||||
|
||||
.. _cva6_riscv_instructions_RVZicond:
|
||||
|
||||
*Applicability of this chapter to configurations:*
|
||||
|
||||
.. csv-table::
|
||||
:widths: auto
|
||||
:align: left
|
||||
:header: "Configuration", "Implementation"
|
||||
|
||||
"CV32A60X", "Implemented extension"
|
||||
"CV32E6?X", "Not implemented extension"
|
||||
|
||||
**Note**: RV32Zicond and RV64Zicond are identical.
|
||||
|
||||
|
||||
RVZicond Integer Conditional operations
|
||||
-------------------------------------------
|
||||
|
||||
The instructions follow the format for R-type instructions with 3 operands (i.e., 2 source operands and 1 destination operand). Using these instructions, branchless sequences can be implemented (typically in two-instruction sequences) without the need for instruction fusion, special provisions during the decoding of architectural instructions, or other microarchitectural provisions.
|
||||
|
||||
- **CZERO.EQZ**: Conditional zero, if condition is equal to zero
|
||||
|
||||
**Format**: czero.eqz rd, rs1, rs2
|
||||
|
||||
**Description**: This instruction behaves as if there is a conditional branch dependent on rs2 being equal to zero, wherein it branches to code that writes a 0 into rd when the equivalence is true, and otherwise falls through to code that moves rs1 into rd.
|
||||
|
||||
**Pseudocode**: if (x[rs2] == 0) x[rd] = 0 else x[rs1]
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
- **CZERO.NEZ**: Conditional zero, if condition is nonzero
|
||||
|
||||
**Format**: czero.nez rd, rs1, rs2
|
||||
|
||||
**Description**: This instruction behaves as if there is a conditional branch dependent on rs2 being not equal to zero, wherein it branches to code that writes a 0 into rd when the equivalence is true, and otherwise falls through to code that moves rs1 into rd
|
||||
|
||||
**Pseudocode**: if (x[rs2] != 0) x[rd] = 0 else x[rs1]
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
102
docs/01_cva6_user/RISCV_Instructions_RVZicsr.rst
Normal file
102
docs/01_cva6_user/RISCV_Instructions_RVZicsr.rst
Normal file
|
|
@ -0,0 +1,102 @@
|
|||
..
|
||||
Copyright (c) 2023 OpenHW Group
|
||||
Copyright (c) 2023 Thales
|
||||
|
||||
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
.. Level 1
|
||||
=======
|
||||
|
||||
Level 2
|
||||
-------
|
||||
|
||||
Level 3
|
||||
~~~~~~~
|
||||
|
||||
Level 4
|
||||
^^^^^^^
|
||||
|
||||
.. _cva6_riscv_instructions_RVZicsr:
|
||||
|
||||
*Applicability of this chapter to configurations:*
|
||||
|
||||
This chapter is applicable to all CVA6 configurations.
|
||||
|
||||
**Note**: RV32Zicsr and RV64Zicsr are identical.
|
||||
|
||||
RVZicsr Control and Status Register Instructions
|
||||
---------------------------------------------------
|
||||
|
||||
All CSR instructions atomically read-modify-write a single CSR, whose CSR specifier is encoded in the 12-bit csr field of the instruction held in bits 31–20. The immediate forms use a 5-bit zero-extended immediate encoded in the rs1 field.
|
||||
|
||||
- **CSRRW**: Control and Status Register Read and Write
|
||||
|
||||
**Format**: csrrw rd, csr, rs1
|
||||
|
||||
**Description**: reads the old value of the CSR, zero-extends the value to 32 bits, then writes it to integer register rd, the initial value in rs1 is written to the CSR. If rd=x0, then the instruction shall not read the CSR and shall not cause any of the side-effects that might occur on a CSR read.
|
||||
|
||||
**Pseudocode**: t = CSRs[csr]; CSRs[csr] = x[rs1]; x[rd] = t
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: attempts to access a non-existent CSR raise an illegal instruction exception, attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions.
|
||||
|
||||
- **CSRRS**: Control and Status Register Read and Set
|
||||
|
||||
**Format**: csrrs rd, csr, rs1
|
||||
|
||||
**Description**: reads the value of the CSR, zero-extends the value to 32 bits, and writes it to integer register rd, the initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be set in the CSR. Any bit that is high in rs1 will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. Other bits in the CSR are unaffected (though CSRs might have side effects when written), if rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects that might otherwise occur on a CSR write, such as raising illegal instruction exceptions on accesses to read-only CSRs.
|
||||
|
||||
**Pseudocode**: t = CSRs[csr]; CSRs[csr] = t | x[rs1]; x[rd] = t
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: attempts to access a non-existent CSR raise an illegal instruction exception, attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions.
|
||||
|
||||
- **CSRRC**: Control and Status Register Read and Clear
|
||||
|
||||
**Format**: csrrc rd, csr, rs1
|
||||
|
||||
**Description**: reads the value of the CSR, zero-extends the value to 32 bits, and writes it to integer register rd, the initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be cleared in the CSR. Any bit that is high in rs1 will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. Other bits in the CSR are unaffected (though CSRs might have side effects when written), if rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects that might otherwise occur on a CSR write, such as raising illegal instruction exceptions on accesses to read-only CSRs.
|
||||
|
||||
**Pseudocode**: t = CSRs[csr]; CSRs[csr] = t & ∼x[rs1]; x[rd] = t
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: attempts to access a non-existent CSR raise an illegal instruction exception, attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions.
|
||||
|
||||
- **CSRRWI**: Control and Status Register Read and Write Immediate
|
||||
|
||||
**Format**: csrrwi rd, csr, uimm[4:0]
|
||||
|
||||
**Description**: reads the old value of the CSR, zero-extends the value to 32 bits, then writes it to integer register rd. The zero-extends immediate is written to the CSR. If rd=x0, then the instruction shall not read the CSR and shall not cause any of the side-effects that might occur on a CSR read.
|
||||
|
||||
**Pseudocode**: x[rd] = CSRs[csr]; CSRs[csr] = zext(uimm[4:0])
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: attempts to access a non-existent CSR raise an illegal instruction exception, attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions.
|
||||
|
||||
- **CSRRSI**: Control and Status Register Read and Set Immediate
|
||||
|
||||
**Format**: csrrsi rd, csr, uimm[4:0]
|
||||
|
||||
**Description**: reads the value of the CSR, zero-extends the value to 32 bits, and writes it to integer register rd. The zero-extends immediate value is treated as a bit mask that specifies bit positions to be set in the CSR. Any bit that is high in zero-extends immediate will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. Other bits in the CSR are unaffected (though CSRs might have side effects when written), if the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write.
|
||||
|
||||
**Pseudocode**: t = CSRs[csr]; CSRs[csr] = t | zext(uimm[4:0]); x[rd] = t
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: attempts to access a non-existent CSR raise an illegal instruction exception, attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions.
|
||||
|
||||
- **CSRRCI**: Control and Status Register Read and Clear Immediate
|
||||
|
||||
**Format**: csrrci rd, csr, uimm[4:0]
|
||||
|
||||
**Description**: reads the value of the CSR, zero-extends the value to 32 bits, and writes it to integer register rd. The zero-extends immediate value is treated as a bit mask that specifies bit positions to be cleared in the CSR. Any bit that is high in zero-extends immediate will cause the corresponding bit to be set in the CSR, if that CSR bit is writable. Other bits in the CSR are unaffected (though CSRs might have side effects when written), if the uimm[4:0] field is zero, then these instructions will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on a CSR write.
|
||||
|
||||
**Pseudocode**: t = CSRs[csr]; CSRs[csr] = t & ∼zext(uimm[4:0]); x[rd] = t
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: attempts to access a non-existent CSR raise an illegal instruction exception, attempts to access a CSR without appropriate privilege level or to write a read-only register also raise illegal instruction exceptions.
|
||||
42
docs/01_cva6_user/RISCV_Instructions_RVZifencei.rst
Normal file
42
docs/01_cva6_user/RISCV_Instructions_RVZifencei.rst
Normal file
|
|
@ -0,0 +1,42 @@
|
|||
..
|
||||
Copyright (c) 2023 OpenHW Group
|
||||
Copyright (c) 2023 Thales
|
||||
|
||||
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
.. Level 1
|
||||
=======
|
||||
|
||||
Level 2
|
||||
-------
|
||||
|
||||
Level 3
|
||||
~~~~~~~
|
||||
|
||||
Level 4
|
||||
^^^^^^^
|
||||
|
||||
.. _cva6_riscv_instructions_RVZifencei:
|
||||
|
||||
*Applicability of this chapter to configurations:*
|
||||
|
||||
This chapter is applicable to all CVA6 configurations.
|
||||
|
||||
**Note**: RV32Zifencei and RV64Zifencei are identical.
|
||||
|
||||
|
||||
RVZifencei Instruction-Fetch Fence
|
||||
--------------------------------------
|
||||
|
||||
- **FENCE.I**: Fence Instruction
|
||||
|
||||
**Format**: fence.i
|
||||
|
||||
**Description**: The FENCE.I instruction is used to synchronize the instruction and data streams. RISC-V does not guarantee that stores to instruction memory will be made visible to instruction fetches on the same RISC-V hart until a FENCE.I instruction is executed. A FENCE.I instruction only ensures that a subsequent instruction fetch on a RISC-V hart will see any previous data stores already visible to the same RISC-V hart.
|
||||
|
||||
**Pseudocode**: Fence(Store, Fetch)
|
||||
|
||||
**Invalid values**: NONE
|
||||
|
||||
**Exception raised**: NONE
|
||||
|
||||
|
|
@ -1,44 +1,52 @@
|
|||
..
|
||||
Copyright (c) 2023 OpenHW Group
|
||||
Copyright (c) 2023 Thales DIS design services SAS
|
||||
|
||||
Licensed under the Solderpad Hardware Licence, Version 2.1 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
https://solderpad.org/licenses/
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
|
||||
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
CVA6 User Manual
|
||||
================
|
||||
Editor: **Jerome Quevremont**
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 2
|
||||
:caption: Contents:
|
||||
|
||||
CVA6_user_guide
|
||||
Introduction
|
||||
Programmer_View
|
||||
Custom_Instructions
|
||||
PMA
|
||||
PMP
|
||||
Traps_Interrupts_Exceptions
|
||||
Compiler_Command_Lines
|
||||
RISCV_Instructions
|
||||
CV32A6_Control_Status_Registers
|
||||
CV64A6_Control_Status_Registers
|
||||
CSR_Cache_Control
|
||||
CSR_Performance_Counters
|
||||
Parameters_Configuration
|
||||
Interfaces
|
||||
Core_Integration
|
||||
CVX_Interface_Coprocessor
|
||||
AXI_Interface
|
||||
..
|
||||
Copyright (c) 2023 OpenHW Group
|
||||
Copyright (c) 2023 Thales DIS design services SAS
|
||||
|
||||
Licensed under the Solderpad Hardware Licence, Version 2.1 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
https://solderpad.org/licenses/
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
|
||||
SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
CVA6 User Manual
|
||||
================
|
||||
Editor: **Jerome Quevremont**
|
||||
|
||||
.. toctree::
|
||||
:maxdepth: 2
|
||||
:caption: Contents:
|
||||
|
||||
CVA6_user_guide
|
||||
Introduction
|
||||
Programmer_View
|
||||
Custom_Instructions
|
||||
PMA
|
||||
PMP
|
||||
Traps_Interrupts_Exceptions
|
||||
Compiler_Command_Lines
|
||||
RISCV_Instructions
|
||||
RISCV_Instructions_RV32I
|
||||
RISCV_Instructions_RV32M
|
||||
RISCV_Instructions_RV32A
|
||||
RISCV_Instructions_RV32C
|
||||
RISCV_Instructions_RV32ZCb
|
||||
RISCV_Instructions_RVZicsr
|
||||
RISCV_Instructions_RVZifencei
|
||||
RISCV_Instructions_RVZicond
|
||||
CV32A6_Control_Status_Registers
|
||||
CV64A6_Control_Status_Registers
|
||||
CSR_Cache_Control
|
||||
CSR_Performance_Counters
|
||||
Parameters_Configuration
|
||||
Interfaces
|
||||
Core_Integration
|
||||
CVX_Interface_Coprocessor
|
||||
AXI_Interface
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue