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Initialize instruction traced shadow regfile to zero at start of simulation

Browse source 
Fix progbuf offsets and tie unsupported counters to zero to avoid propagation of X

Fix printouts of assertions

Modify bootrom to prevent assignment of X to output
This commit is contained in:
Michael Schaffner 2018-10-12 14:47:47 +02:00
parent 15b0ca956a
commit 6eb56f9893
No known key found for this signature in database
GPG key ID: 7AA09AE049819C2C
8 changed files with 150 additions and 118 deletions
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bootrom/bootrom.img
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164
bootrom/bootrom.sv
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@ -1,10 +1,10 @@
/* Copyright 2018 ETH Zurich and University of Bologna.
* Copyright and related rights are licensed under the Solderpad Hardware
* License, Version 0.51 (the “License”); you may not use this file except in
* License, Version 0.51 (the "License"); you may not use this file except in
* compliance with the License. You may obtain a copy of the License at
* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
* or agreed to in writing, software, hardware and materials distributed under
* this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
* this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
* CONDITIONS OF ANY KIND, either express or implied. See the License for the
* specific language governing permissions and limitations under the License.
*
@ -20,152 +20,150 @@ module bootrom (
input logic [63:0] addr_i,
output logic [63:0] rdata_o
);
localparam int RomSize = 143;
localparam int RomSize = 141;
const logic [RomSize-1:0][63:0] mem = {
64'h00646564_6e657478,
64'h652d7374_70757272,
64'h65746e69_00736567,
64'h6e617200_656c646e,
64'h6168702c_78756e69,
64'h6c007265_6c6c6f72,
64'h746e6f63_2d747075,
64'h72726574_6e690073,
64'h6c6c6563_2d747075,
64'h72726574_6e692300,
64'h79636e65_75716572,
64'h662d6b63_6f6c6300,
64'h65707974_2d756d6d,
64'h00617369_2c766373,
64'h00000000_00000064,
64'h65646E65_7478652D,
64'h73747075_72726574,
64'h6E690073_65676E61,
64'h7200656C_646E6168,
64'h70007265_6C6C6F72,
64'h746E6F63_2D747075,
64'h72726574_6E690073,
64'h6C6C6563_2D747075,
64'h72726574_6E692300,
64'h79636E65_75716572,
64'h662D6B63_6F6C6300,
64'h65707974_2D756D6D,
64'h00617369_2C766373,
64'h69720073_75746174,
64'h73006765_72006570,
64'h79745f65_63697665,
64'h64007963_6e657571,
64'h6572662d_65736162,
64'h656d6974_006c6564,
64'h6f6d0065_6c626974,
64'h61706d6f_6300736c,
64'h6c65632d_657a6973,
64'h2300736c_6c65632d,
64'h79745F65_63697665,
64'h64007963_6E657571,
64'h6572662D_65736162,
64'h656D6974_006C6564,
64'h6F6D0065_6C626974,
64'h61706D6F_6300736C,
64'h6C65632D_657A6973,
64'h2300736C_6C65632D,
64'h73736572_64646123,
64'h09000000_02000000,
64'h02000000_00000030,
64'h66697468_2c626375,
64'h1b000000_0a000000,
64'h66697468_2C626375,
64'h1B000000_0A000000,
64'h03000000_00000000,
64'h66697468_01000000,
64'h02000000_02000000,
64'h00000c00_00000000,
64'h00000C00_00000000,
64'h00000002_00000000,
64'h4b000000_10000000,
64'h4B000000_10000000,
64'h03000000_07000000,
64'h01000000_03000000,
64'h01000000_b4000000,
64'h01000000_AE000000,
64'h10000000_03000000,
64'h00000000_30746e69,
64'h6c632c76_63736972,
64'h1b000000_0d000000,
64'h00000000_30746E69,
64'h6C632C76_63736972,
64'h1B000000_0D000000,
64'h03000000_00000030,
64'h30303030_30324074,
64'h6e696c63_01000000,
64'had000000_00000000,
64'h6E696C63_01000000,
64'hA7000000_00000000,
64'h03000000_00007375,
64'h622d656c_706d6973,
64'h00636f73_2d657261,
64'h622d656e_61697261,
64'h2c687465_1b000000,
64'h1f000000_03000000,
64'h02000000_0f000000,
64'h622D656C_706D6973,
64'h00636F73_2D657261,
64'h622D656E_61697261,
64'h2C687465_1B000000,
64'h1F000000_03000000,
64'h02000000_0F000000,
64'h04000000_03000000,
64'h02000000_00000000,
64'h04000000_03000000,
64'h00636f73_01000000,
64'h00636F73_01000000,
64'h02000000_00000001,
64'h00000000_00000080,
64'h00000000_4b000000,
64'h00000000_4B000000,
64'h10000000_03000000,
64'h00007972_6f6d656d,
64'h3f000000_07000000,
64'h00007972_6F6D656D,
64'h3F000000_07000000,
64'h03000000_00303030,
64'h30303030_38407972,
64'h6f6d656d_01000000,
64'h6F6D656D_01000000,
64'h02000000_02000000,
64'h02000000_01000000,
64'ha5000000_04000000,
64'h03000000_01000000,
64'h9f000000_04000000,
64'h9F000000_04000000,
64'h03000000_00006374,
64'h6e692d75_70632c76,
64'h63736972_1b000000,
64'h0f000000_03000000,
64'h8a000000_00000000,
64'h6E692D75_70632C76,
64'h63736972_1B000000,
64'h0F000000_03000000,
64'h8A000000_00000000,
64'h03000000_01000000,
64'h79000000_04000000,
64'h03000000_00000000,
64'h72656c6c_6f72746e,
64'h6f632d74_70757272,
64'h65746e69_01000000,
64'h00ca9a3b_69000000,
64'h72656C6C_6F72746E,
64'h6F632D74_70757272,
64'h65746E69_01000000,
64'h00CA9A3B_69000000,
64'h04000000_03000000,
64'h00003933_76732c76,
64'h00003933_76732C76,
64'h63736972_60000000,
64'h0b000000_03000000,
64'h00636d69_34367672,
64'h0B000000_03000000,
64'h00636D69_34367672,
64'h56000000_08000000,
64'h03000000_00000076,
64'h63736972_1b000000,
64'h63736972_1B000000,
64'h06000000_03000000,
64'h00000000_79616b6f,
64'h4f000000_05000000,
64'h00000000_79616B6F,
64'h4F000000_05000000,
64'h03000000_00000000,
64'h4b000000_04000000,
64'h4B000000_04000000,
64'h03000000_00757063,
64'h3f000000_04000000,
64'h3F000000_04000000,
64'h03000000_00000030,
64'h40757063_01000000,
64'h80969800_2c000000,
64'h80969800_2C000000,
64'h04000000_03000000,
64'h00000000_0f000000,
64'h00000000_0F000000,
64'h04000000_03000000,
64'h01000000_00000000,
64'h04000000_03000000,
64'h00000000_73757063,
64'h01000000_00657261,
64'h622d656e_61697261,
64'h2c687465_26000000,
64'h622D656E_61697261,
64'h2C687465_26000000,
64'h10000000_03000000,
64'h00766564_2d657261,
64'h622d656e_61697261,
64'h2c687465_1b000000,
64'h00766564_2D657261,
64'h622D656E_61697261,
64'h2C687465_1B000000,
64'h14000000_03000000,
64'h02000000_0f000000,
64'h02000000_0F000000,
64'h04000000_03000000,
64'h02000000_00000000,
64'h04000000_03000000,
64'h00000000_01000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'hf8020000_c8000000,
64'hE8020000_C2000000,
64'h00000000_10000000,
64'h11000000_28000000,
64'h30030000_38000000,
64'hf8030000_edfe0dd0,
64'h20030000_38000000,
64'hE2030000_EDFE0DD0,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_0000bff5,
64'h10500073_03c58593,
64'h00000597_f1402573,
64'h00000000_0000BFF5,
64'h10500073_03C58593,
64'h00000597_F1402573,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00008402_07458593,
64'h00000597_f1402573,
64'h01f41413_0010041b
64'h00000597_F1402573,
64'h01F41413_0010041B
};
logic [$clog2(RomSize)-1:0] addr_q;
@ -176,5 +174,7 @@ module bootrom (
end
end
assign rdata_o = mem[addr_q];
// this prevents spurious Xes from propagating into
// the speculative fetch stage of the core
assign rdata_o = (addr_q<RomSize) ? mem[addr_q] : '0;
endmodule

12
bootrom/gen_rom.py
View file

@ -22,11 +22,11 @@ filename = os.path.splitext(file)[0]
license = """\
/* Copyright 2018 ETH Zurich and University of Bologna.
* Copyright and related rights are licensed under the Solderpad Hardware
* License, Version 0.51 (the “License”); you may not use this file except in
* License, Version 0.51 (the "License"); you may not use this file except in
* compliance with the License. You may obtain a copy of the License at
* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
* or agreed to in writing, software, hardware and materials distributed under
* this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
* this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
* CONDITIONS OF ANY KIND, either express or implied. See the License for the
* specific language governing permissions and limitations under the License.
*
@ -59,7 +59,9 @@ module $filename (
end
end
assign rdata_o = mem[addr_q];
// this prevents spurious Xes from propagating into
// the speculative fetch stage of the core
assign rdata_o = (addr_q<RomSize) ? mem[addr_q] : '0;
endmodule
"""
@ -75,11 +77,11 @@ with open(filename + ".img", "rb") as f:
if i == 4:
word = "_" + word
if byte:
word = byte.hex() + word
word = ("%02X" % int.from_bytes(byte, "little")) + word
# fill up with zeros if unaligned
else:
pass
# word += "00";
word = "00" + word;
if word != "_":
word = "64'h" + word

24
src/cache_subsystem/std_cache_subsystem.sv
View file

@ -104,22 +104,22 @@ module std_cache_subsystem #(
`ifndef VERILATOR
a_invalid_instruction_fetch: assert property (
@(posedge clk_i) disable iff (~rst_ni) icache_dreq_o.valid |-> (|icache_dreq_o.data) !== 1'hX)
else $warning(1,"[l1 dcache] reading invalid instructions: vaddr=%016X, data=%016X",
icache_dreq_o.vaddr, icache_dreq_o.data);
@(posedge clk_i) disable iff (~rst_ni) icache_dreq_o.valid |-> (|icache_dreq_o.data) !== 1'hX)
else $warning(1,"[l1 dcache] reading invalid instructions: vaddr=%08X, data=%08X",
icache_dreq_o.vaddr, icache_dreq_o.data);
a_invalid_write_data: assert property (
@(posedge clk_i) disable iff (~rst_ni) dcache_req_ports_i[2].data_req |-> |dcache_req_ports_i[2].data_be |-> (|dcache_req_ports_i[2].data_wdata) !== 1'hX)
else $warning(1,"[l1 dcache] writing invalid data: paddr=%016X, be=%02X, data=%016X",
{dcache_req_ports_i[2].address_tag, dcache_req_ports_i[2].address_index}, dcache_req_ports_i[2].data_be, dcache_req_ports_i[2].data_wdata);
@(posedge clk_i) disable iff (~rst_ni) dcache_req_ports_i[2].data_req |-> |dcache_req_ports_i[2].data_be |-> (|dcache_req_ports_i[2].data_wdata) !== 1'hX)
else $warning(1,"[l1 dcache] writing invalid data: paddr=%016X, be=%02X, data=%016X",
{dcache_req_ports_i[2].address_tag, dcache_req_ports_i[2].address_index}, dcache_req_ports_i[2].data_be, dcache_req_ports_i[2].data_wdata);
generate
for(genvar j=0; j<2; j++) begin
a_invalid_read_data: assert property (
@(posedge clk_i) disable iff (~rst_ni) dcache_req_ports_o[j].data_rvalid |-> (|dcache_req_ports_o[j].data_rdata) !== 1'hX)
else $warning(1,"[l1 dcache] reading invalid data on port %01d: data=%016X",
j, dcache_req_ports_o[j].data_rdata);
end
endgenerate
a_invalid_read_data: assert property (
@(posedge clk_i) disable iff (~rst_ni) dcache_req_ports_o[j].data_rvalid |-> (|dcache_req_ports_o[j].data_rdata) !== 1'hX)
else $warning(1,"[l1 dcache] reading invalid data on port %01d: data=%016X",
j, dcache_req_ports_o[j].data_rdata);
end
endgenerate
`endif
//pragma translate_on

29
src/debug/debug_rom/debug_rom.sv
View file

@ -1,10 +1,10 @@
/* Copyright 2018 ETH Zurich and University of Bologna.
* Copyright and related rights are licensed under the Solderpad Hardware
* License, Version 0.51 (the “License”); you may not use this file except in
* License, Version 0.51 (the "License"); you may not use this file except in
* compliance with the License. You may obtain a copy of the License at
* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
* or agreed to in writing, software, hardware and materials distributed under
* this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
* this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
* CONDITIONS OF ANY KIND, either express or implied. See the License for the
* specific language governing permissions and limitations under the License.
*
@ -20,21 +20,22 @@ module debug_rom (
input logic [63:0] addr_i,
output logic [63:0] rdata_o
);
localparam int RomSize = 12;
localparam int RomSize = 13;
const logic [RomSize-1:0][63:0] mem = {
64'h7b200073_7b202473,
64'h10802423_f1402473,
64'h00000000_00000000,
64'h7B200073_7B202473,
64'h10802423_F1402473,
64'h30000067_10002223,
64'h7b202473_00100073,
64'h10002623_fddff06f,
64'hfc0418e3_00247413,
64'h40044403_f1402473,
64'h7B202473_00100073,
64'h10002623_FDDFF06F,
64'hFC0418E3_00247413,
64'h40044403_F1402473,
64'h02041063_00147413,
64'h40044403_10802023,
64'hf1402473_7b241073,
64'h0ff0000f_0340006f,
64'h04c0006f_00c0006f
64'hF1402473_7B241073,
64'h0FF0000F_0340006F,
64'h04C0006F_00C0006F
};
logic [$clog2(RomSize)-1:0] addr_q;
@ -45,5 +46,7 @@ module debug_rom (
end
end
assign rdata_o = mem[addr_q];
// this prevents spurious Xes from propagating into
// the speculative fetch stage of the core
assign rdata_o = (addr_q<RomSize) ? mem[addr_q] : '0;
endmodule

35
src/debug/dm_csrs.sv
View file

@ -90,6 +90,11 @@ module dm_csrs #(
logic [31:0] haltsum0, haltsum1, haltsum2, haltsum3;
// TODO(zarubaf) Need an elegant way to calculate haltsums
// remove assertions below when implemented...
assign haltsum0 = '0;
assign haltsum1 = '0;
assign haltsum2 = '0;
assign haltsum3 = '0;
for (genvar i = 0; i < 32; i++) begin
// assign haltsum0[i] = halted_i[i];
// TODO(zarubaf) Implement correct haltsum logic
@ -201,7 +206,7 @@ module dm_csrs #(
end
if (!cmdbusy_i) begin
// check whether we need to re-execute the command (just give a cmd_valid)
cmd_valid_o = abstractauto_q.autoexecdata[dmi_req_i.addr[3:0] - dm::Data0];
cmd_valid_o = abstractauto_q.autoexecdata[dmi_req_i.addr[3:0] - int'(dm::Data0)];
end
end
dm::DMControl: resp_queue_data = dmcontrol_q;
@ -215,7 +220,8 @@ module dm_csrs #(
resp_queue_data = progbuf_q[dmi_req_i.addr[4:0]];
if (!cmdbusy_i) begin
// check whether we need to re-execute the command (just give a cmd_valid)
cmd_valid_o = abstractauto_q.autoexecprogbuf[dmi_req_i.addr[3:0]];
// TODO(zarubaf): check if offset is correct - without it this may assign Xes
cmd_valid_o = abstractauto_q.autoexecprogbuf[dmi_req_i.addr[3:0]+16];
end
end
dm::HaltSum0: resp_queue_data = haltsum0;
@ -272,7 +278,7 @@ module dm_csrs #(
if (!cmdbusy_i && dm::DataCount > 0) begin
data_d[dmi_req_i.addr[4:0]] = dmi_req_i.data;
// check whether we need to re-execute the command (just give a cmd_valid)
cmd_valid_o = abstractauto_q.autoexecdata[dmi_req_i.addr[3:0] - dm::Data0];
cmd_valid_o = abstractauto_q.autoexecdata[dmi_req_i.addr[3:0] - int'(dm::Data0)];
end
end
dm::DMControl: begin
@ -327,7 +333,8 @@ module dm_csrs #(
progbuf_d[dmi_req_i.addr[4:0]] = dmi_req_i.data;
// check whether we need to re-execute the command (just give a cmd_valid)
// this should probably throw an error if executed during another command was busy
cmd_valid_o = abstractauto_q.autoexecprogbuf[dmi_req_i.addr[3:0]];
// TODO(zarubaf): check if offset is correct - without it this may assign Xes
cmd_valid_o = abstractauto_q.autoexecprogbuf[dmi_req_i.addr[3:0]+16];
end
end
dm::SBCS: begin
@ -508,4 +515,24 @@ module dm_csrs #(
end
end
end
///////////////////////////////////////////////////////
// assertions
///////////////////////////////////////////////////////
//pragma translate_off
`ifndef VERILATOR
haltsum: assert property (
@(posedge clk_i) disable iff (~rst_ni) (dmi_req_ready_o && dmi_req_valid_i && dtm_op == dm::DTM_READ) |->
!({1'b0, dmi_req_i.addr} inside {dm::HaltSum0, dm::HaltSum1, dm::HaltSum2, dm::HaltSum3}))
else $warning("Haltsums are not implemented yet and always return 0.");
`endif
//pragma translate_on
endmodule

2
src/debug/dm_top.sv
View file

@ -48,7 +48,7 @@ module dm_top #(
// Debug CSRs
dm::hartinfo_t [NrHarts-1:0] hartinfo;
logic [NrHarts-1:0] halted;
logic [NrHarts-1:0] running;
// logic [NrHarts-1:0] running;
logic [NrHarts-1:0] resumeack;
logic [NrHarts-1:0] haltreq;
logic [NrHarts-1:0] resumereq;

2
src/util/instruction_tracer.svh
View file

@ -60,7 +60,7 @@ class instruction_tracer;
logic [31:0] decode_instruction, issue_instruction, issue_commit_instruction;
scoreboard_entry_t commit_instruction;
// initialize register 0
reg_file [0] = 0;
reg_file = '{default:0};
forever begin
automatic branchpredict_t bp_instruction = '0;