Fixes Issue #15

ariane.sv

@@ -135,6 +135,7 @@ module ariane
         .flush_i             ( flush_i                      ),
         .instruction_i       ( instr_rdata_id_o             ),
         .instruction_valid_i ( instr_valid_id_o             ),
+        .is_compressed_i     ( is_compressed_id_o           ),
         .pc_if_i             ( pc_if_o                      ), // PC from if
         .ex_i                ( exception_if                 ), // exception from if
         .ready_o             ( ready_o                      ),

commit_stage.sv

@@ -31,6 +31,7 @@ module commit_stage (
     assign wdata_a_o = commit_instr_i.result;
 
     // commit instruction
+    // write register file
     always_comb begin : commit
         // default assignments
         commit_ack_o = 1'b0;
@@ -41,8 +42,6 @@ module commit_stage (
         end
     end
 
-    // write register file
-
     // CSR logic
 
     // privilege check

decoder.sv

@@ -11,12 +11,13 @@
 import ariane_pkg::*;
 
 module decoder (
-    input  logic            clk_i,          // Clock
-    input  logic            rst_ni,         // Asynchronous reset active low
-    input  logic [63:0]     pc_i,           // PC from IF
-    input  logic [31:0]     instruction_i,  // instruction from IF
-    input  exception        ex_i,           // if an exception occured in if
-    output scoreboard_entry instruction_o,  // scoreboard entry to scoreboard
+    input  logic            clk_i,           // Clock
+    input  logic            rst_ni,          // Asynchronous reset active low
+    input  logic [63:0]     pc_i,            // PC from IF
+    input  logic            is_compressed_i, // is a compressed instruction
+    input  logic [31:0]     instruction_i,   // instruction from IF
+    input  exception        ex_i,            // if an exception occured in if
+    output scoreboard_entry instruction_o,   // scoreboard entry to scoreboard
     output logic            illegal_instr_o
 );
     instruction instr;
@@ -48,6 +49,7 @@ module decoder (
         instruction_o.rd = 5'b0;
         instruction_o.use_pc = 1'b0;
         instruction_o.trans_id = 5'b0;
+        instruction_o.is_compressed = is_compressed_i;
         // TODO end
         if (~ex_i.valid) begin
             case (instr.rtype.opcode)

id_stage.sv

@@ -22,6 +22,7 @@ module id_stage #(
     // from IF
     input  logic [31:0]                              instruction_i,
     input  logic                                     instruction_valid_i,
+    input  logic                                     is_compressed_i,
     input  logic [63:0]                              pc_if_i,
     input  exception                                 ex_i,
     output logic                                     ready_o,   // id is ready
@@ -75,6 +76,7 @@ module id_stage #(
         .clk_i           ( clk_i            ),
         .rst_ni          ( rst_ni           ),
         .pc_i            ( pc_if_i          ),
+        .is_compressed_i ( is_compressed_i  ),
         .instruction_i   ( instruction_i    ),
         .ex_i            ( ex_i             ),
         .instruction_o   ( decoded_instr_i  ),

include/ariane_pkg.svh

@@ -57,18 +57,20 @@ package ariane_pkg;
     // ID/EX/WB Stage
     // ---------------
     typedef struct packed {
-        logic [TRANS_ID_BITS-1:0]     trans_id; // this can potentially be simplified, we could index the scoreboard entry
-                                                // with the transaction id in any case make the width more generic
-        fu_t                          fu;       // functional unit to use
-        fu_op                         op;       // operation to perform in each functional unit
-        logic [4:0]                   rs1;      // register source address 1
-        logic [4:0]                   rs2;      // register source address 2
-        logic [4:0]                   rd;       // register destination address
-        logic [63:0]                  result;   // for unfinished instructions this field also holds the immediate
-        logic                         valid;    // is the result valid
-        logic                         use_imm;  // should we use the immediate as operand b?
-        logic                         use_pc;   // set if we need to use the PC as operand A, PC from exception
-        exception                     ex;       // exception has occurred
+        logic [TRANS_ID_BITS-1:0]     trans_id;      // this can potentially be simplified, we could index the scoreboard entry
+                                                     // with the transaction id in any case make the width more generic
+        fu_t                          fu;            // functional unit to use
+        fu_op                         op;            // operation to perform in each functional unit
+        logic [4:0]                   rs1;           // register source address 1
+        logic [4:0]                   rs2;           // register source address 2
+        logic [4:0]                   rd;            // register destination address
+        logic [63:0]                  result;        // for unfinished instructions this field also holds the immediate
+        logic                         valid;         // is the result valid
+        logic                         use_imm;       // should we use the immediate as operand b?
+        logic                         use_pc;        // set if we need to use the PC as operand A, PC from exception
+        exception                     ex;            // exception has occurred
+        logic                         is_compressed; // signals a compressed instructions, we need this information at the commit stage if
+                                                     // we want jump accordingly e.g.: +4, +2
     } scoreboard_entry;
 
     // --------------------