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Fix issue #2479 #2468 (#2318)

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Jalali 2024-07-03 15:14:15 +00:00 • committed by GitHub
parent ace1643e91
commit 702fedf23f
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3 changed files with 17 additions and 2 deletions
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2
verif/core-v-verif

@ -1 +1 @@
Subproject commit 4531071c3c8868e09e00848058f4a8e6f2e5188a
Subproject commit 1173e7e1b780ad10c4c6c4a8e35a5d4a305e50e8

3
verif/env/uvme/uvme_cva6_cfg.sv vendored
View file

@ -155,6 +155,9 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
dm_exception_addr_valid == 1;
nmi_addr_valid == 1;
HPDCache_supported == (CVA6Cfg.DCacheType == 2);
DirectVecOnly == CVA6Cfg.DirectVecOnly;
TvalEn == CVA6Cfg.TvalEn;
}
constraint ext_const {

14
verif/tb/core/uvma_cva6pkg_utils.sv
View file

@ -55,6 +55,9 @@ function st_core_cntrl_cfg cva6pkg_to_core_cntrl_cfg(st_core_cntrl_cfg cfg);
cfg.pmp_regions = CVA6Cfg.NrPMPEntries;
cfg.debug_supported = CVA6Cfg.DebugEn;
cfg.DirectVecOnly = CVA6Cfg.DirectVecOnly;
cfg.TvalEn = CVA6Cfg.TvalEn;
cfg.unsupported_csr_mask['h643] = 1; // HTVAL
cfg.unsupported_csr_mask['h64A] = 1; // HTINST
@ -78,13 +81,22 @@ function st_core_cntrl_cfg cva6pkg_to_core_cntrl_cfg(st_core_cntrl_cfg cfg);
void'(spike_set_param_str(base, "extensions", "cv32a60x"));
// All enabled except XS and TW bits
void'(spike_set_param_uint64_t(base, "mstatus_write_mask", 'hFDFE_7FFF));
void'(spike_set_param_uint64_t(base, "mstatus_write_mask", 'hFFDE_7FFF));
if (cfg.DirectVecOnly) begin
void'(spike_set_param_uint64_t(base, "mtvec_write_mask", 32'hFFFF_FFFC));
end
void'(spike_set_param_uint64_t(base, "misa_override_value", get_misa(cfg)));
void'(spike_set_param_uint64_t(base, "misa_override_mask", 64'h0FFF_FFFF));
void'(spike_set_param_bool (base, "misa_we_enable", 1'b1));
void'(spike_set_param_bool (base, "misa_we", 1'b0));
if (!cfg.TvalEn) begin
void'(spike_set_param_bool (base, "mtval_we_enable", 1'b1));
void'(spike_set_param_bool (base, "mtval_we", 1'b0));
end
return cfg;
endfunction : cva6pkg_to_core_cntrl_cfg