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Increase instruction interface to 64 bit

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This commit is contained in:
Florian Zaruba 2017-07-05 15:32:13 +02:00
parent c68a215f41
commit 70e16022a9
9 changed files with 35 additions and 30 deletions
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4
src/ariane.sv
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@ -51,7 +51,7 @@ module ariane
output logic [3:0] instr_if_data_be_o,
input logic instr_if_data_gnt_i,
input logic instr_if_data_rvalid_i,
input logic [31:0] instr_if_data_rdata_i,
input logic [63:0] instr_if_data_rdata_i,
// Data memory interface
output logic [11:0] data_if_address_index_o,
output logic [43:0] data_if_address_tag_o,
@ -196,7 +196,7 @@ module ariane
logic fetch_req_if_ex;
logic fetch_gnt_ex_if;
logic fetch_valid_ex_if;
logic [31:0] fetch_rdata_ex_if;
logic [63:0] fetch_rdata_ex_if;
exception fetch_ex_ex_if;
logic [63:0] fetch_vaddr_if_ex;
// --------------

4
src/ex_stage.sv
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@ -79,7 +79,7 @@ module ex_stage #(
output logic fetch_gnt_o,
output logic fetch_valid_o,
input logic [63:0] fetch_vaddr_i,
output logic [31:0] fetch_rdata_o,
output logic [63:0] fetch_rdata_o,
output exception fetch_ex_o,
input priv_lvl_t priv_lvl_i,
input priv_lvl_t ld_st_priv_lvl_i,
@ -93,7 +93,7 @@ module ex_stage #(
output logic [3:0] instr_if_data_be_o,
input logic instr_if_data_gnt_i,
input logic instr_if_data_rvalid_i,
input logic [31:0] instr_if_data_rdata_i,
input logic [63:0] instr_if_data_rdata_i,
output logic [11:0] data_if_address_index_o,
output logic [43:0] data_if_address_tag_o,

18
src/fetch_fifo.sv
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@ -32,7 +32,7 @@ module fetch_fifo
input branchpredict_sbe branch_predict_i,
input exception ex_i, // fetch exception in
input logic [63:0] in_addr_i,
input logic [31:0] in_rdata_i,
input logic [63:0] in_rdata_i,
input logic in_valid_i,
output logic in_ready_o,
// Dual Port Fetch FIFO
@ -59,6 +59,20 @@ module fetch_fifo
assign full = (status_cnt_q == DEPTH);
assign empty = (status_cnt_q == '0);
// -------------
// Downsize
// -------------
logic [31:0] in_rdata;
// downsize from 64 bit to 32 bit, simply ignore half of the incoming data
always_comb begin : downsize
// take the upper half
if (in_addr_i[2])
in_rdata = in_rdata_i[63:32];
// take the lower half of the instruction
else
in_rdata = in_rdata_i[31:0];
end
always_comb begin : fetch_fifo_logic
// counter
automatic logic [$clog2(DEPTH)-1:0] status_cnt = status_cnt_q;
@ -73,7 +87,7 @@ module fetch_fifo
if (in_valid_i) begin
status_cnt++;
// new input data
mem_n[write_pointer_q] = {in_addr_i, in_rdata_i, branch_predict_i, ex_i};
mem_n[write_pointer_q] = {in_addr_i, in_rdata, branch_predict_i, ex_i};
write_pointer++;
end

2
src/if_stage.sv
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@ -34,7 +34,7 @@ module if_stage (
output logic [63:0] instr_addr_o,
input logic instr_gnt_i,
input logic instr_rvalid_i,
input logic [31:0] instr_rdata_i,
input logic [63:0] instr_rdata_i,
input exception instr_ex_i, // Instruction fetch exception, valid if rvalid is one
// Output of IF Pipeline stage -> Dual Port Fetch FIFO
// output port 0

4
src/lsu.sv
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@ -45,7 +45,7 @@ module lsu #(
output logic fetch_gnt_o, // Instruction fetch interface
output logic fetch_valid_o, // Instruction fetch interface
input logic [63:0] fetch_vaddr_i, // Instruction fetch interface
output logic [31:0] fetch_rdata_o, // Instruction fetch interface
output logic [63:0] fetch_rdata_o, // Instruction fetch interface
output exception fetch_ex_o, // Instruction fetch interface
input priv_lvl_t priv_lvl_i, // From CSR register file
@ -61,7 +61,7 @@ module lsu #(
output logic [3:0] instr_if_data_be_o,
input logic instr_if_data_gnt_i,
input logic instr_if_data_rvalid_i,
input logic [31:0] instr_if_data_rdata_i,
input logic [63:0] instr_if_data_rdata_i,
// Data cache
output logic [11:0] data_if_address_index_o,
output logic [43:0] data_if_address_tag_o,

4
src/mmu.sv
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@ -38,7 +38,7 @@ module mmu #(
output logic fetch_gnt_o,
output logic fetch_valid_o,
input logic [63:0] fetch_vaddr_i,
output logic [31:0] fetch_rdata_o, // pass-through because of interfaces
output logic [63:0] fetch_rdata_o, // pass-through because of interfaces
output exception fetch_ex_o, // write-back fetch exceptions (e.g.: bus faults, page faults, etc.)
// LSU interface
// this is a more minimalistic interface because the actual addressing logic is handled
@ -70,7 +70,7 @@ module mmu #(
output logic [3:0] instr_if_data_be_o,
input logic instr_if_data_gnt_i,
input logic instr_if_data_rvalid_i,
input logic [31:0] instr_if_data_rdata_i,
input logic [63:0] instr_if_data_rdata_i,
// Data memory/cache
output logic [11:0] address_index_o,
output logic [43:0] address_tag_o,

15
tb/common/core_mem.sv
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@ -27,7 +27,7 @@ module core_mem (
input logic [3:0] instr_if_data_be_i,
output logic instr_if_data_gnt_o,
output logic instr_if_data_rvalid_o,
output logic [31:0] instr_if_data_rdata_o,
output logic [63:0] instr_if_data_rdata_o,
// Data memory/cache
input logic [11:0] data_if_address_index_i,
input logic [43:0] data_if_address_tag_i,
@ -45,9 +45,6 @@ module core_mem (
localparam ADDRESS_WIDTH = 16;
logic [ADDRESS_WIDTH-1:0] instr_address;
logic [2:0] instr_address_offset_q;
logic [63:0] instr_data;
logic delayed_instr_request;
// D$ Mock
logic req, we;
logic [7:0] be;
@ -56,13 +53,9 @@ module core_mem (
logic [55:0] data_address;
assign data_address = {data_if_address_tag_i, index[11:3]};
assign delayed_instr_request = instr_if_data_req_i;
// we always grant the request
assign instr_if_data_gnt_o = delayed_instr_request;
assign instr_if_data_gnt_o = instr_if_data_req_i;
assign instr_address = instr_if_address_i[ADDRESS_WIDTH-1+3:3];
// this is necessary as the interface to the dual port memory is 64 bit, but the fetch interface of the core is 32 bit
assign instr_if_data_rdata_o = (instr_address_offset_q[2]) ? instr_data[63:32] : instr_data[31:0];
dp_ram #(
.ADDR_WIDTH ( ADDRESS_WIDTH ),
@ -72,7 +65,7 @@ module core_mem (
.en_a_i ( 1'b1 ),
.addr_a_i ( instr_address ),
.wdata_a_i ( ), // not connected
.rdata_a_o ( instr_data ),
.rdata_a_o ( instr_if_data_rdata_o ),
.we_a_i ( 1'b0 ), // r/o interface
.be_a_i ( ),
// data RAM
@ -111,10 +104,8 @@ module core_mem (
always_ff @(posedge clk_i or negedge rst_ni) begin : proc_
if(~rst_ni) begin
instr_if_data_rvalid_o <= 1'b0;
instr_address_offset_q <= 'b0;
end else begin
instr_if_data_rvalid_o <= instr_if_data_req_i;
instr_address_offset_q <= instr_if_address_i[2:0];
end
end
endmodule

12
tb/common/random_stalls.sv
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@ -26,8 +26,8 @@ module random_stalls
input logic [63:0] core_addr_i,
input logic core_we_i,
input logic [ 3:0] core_be_i,
input logic [31:0] core_wdata_i,
output logic [31:0] core_rdata_o,
input logic [63:0] core_wdata_i,
output logic [63:0] core_rdata_o,
output logic core_rvalid_o,
output logic data_req_o,
@ -35,8 +35,8 @@ module random_stalls
output logic [63:0] data_addr_o,
output logic data_we_o,
output logic [ 3:0] data_be_o,
output logic [31:0] data_wdata_o,
input logic [31:0] data_rdata_i,
output logic [63:0] data_wdata_o,
input logic [63:0] data_rdata_i,
input logic data_rvalid_i
);
@ -50,8 +50,8 @@ module random_stalls
logic [63:0] addr;
logic we;
logic [ 3:0] be;
logic [31:0] wdata;
logic [31:0] rdata;
logic [63:0] wdata;
logic [63:0] rdata;
} stall_mem_t;
mailbox core_reqs = new (4);

2
tb/core_tb.sv
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@ -54,7 +54,7 @@ module core_tb;
logic [3:0] instr_if_data_be;
logic instr_if_data_gnt;
logic instr_if_data_rvalid;
logic [31:0] instr_if_data_rdata;
logic [63:0] instr_if_data_rdata;
logic [11:0] data_if_address_index_i;
logic [43:0] data_if_address_tag_i;