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Remove RVFI_TRACE/RVFI_MEM ifdef verilog directive (#1141)

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To allow to remove optionally ports, ifdef directive are kept in cva6_config package.
This commit is contained in:
JeanRochCoulon 2023-04-11 07:49:59 +02:00 • committed by GitHub
parent 09ed2de0df
commit 710da10297
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GPG key ID: 4AEE18F83AFDEB23
15 changed files with 157 additions and 104 deletions
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7
Makefile
View file

@ -29,7 +29,7 @@ verilator ?= verilator
# traget option
target-options ?=
# additional definess
defines ?= RVFI_TRACE
defines ?=
# test name for torture runs (binary name)
test-location ?= output/test
# set to either nothing or -log
@ -139,7 +139,8 @@ endif
# this list contains the standalone components
src := corev_apu/tb/ariane.sv \
src := core/include/$(target)_config_pkg.sv \
corev_apu/tb/ariane.sv \
$(wildcard corev_apu/bootrom/*.sv) \
$(wildcard corev_apu/clint/*.sv) \
$(wildcard corev_apu/fpga/src/axi2apb/src/*.sv) \
@ -217,7 +218,7 @@ fpga_src := $(wildcard corev_apu/fpga/src/*.sv) $(wildcard corev_apu/fpga/src/b
fpga_src := $(addprefix $(root-dir), $(fpga_src))
# look for testbenches
tbs := corev_apu/tb/ariane_tb.sv corev_apu/tb/ariane_testharness.sv
tbs := core/include/$(target)_config_pkg.sv corev_apu/tb/ariane_tb.sv corev_apu/tb/ariane_testharness.sv
tbs := $(addprefix $(root-dir), $(tbs))
# RISCV asm tests and benchmark setup (used for CI)

104
core/cva6.sv
View file

@ -796,22 +796,6 @@ module cva6 import ariane_pkg::*; #(
// Instruction Tracer
// -------------------
// Instruction trace port (used for FireSim)
`ifdef FIRESIM_TRACE
for (genvar i = 0; i < NR_COMMIT_PORTS; i++) begin : gen_tp_connect
assign trace_o[i].clock = clk_i;
assign trace_o[i].reset = rst_ni;
assign trace_o[i].valid = commit_ack[i] & ~commit_instr_id_commit[i].ex.valid;
assign trace_o[i].iaddr = commit_instr_id_commit[i].pc;
assign trace_o[i].insn = commit_instr_id_commit[i].ex.tval[31:0];
assign trace_o[i].priv = priv_lvl;
assign trace_o[i].exception = commit_ack[i] & commit_instr_id_commit[i].ex.valid & ~commit_instr_id_commit[i].ex.cause[63];
assign trace_o[i].interrupt = commit_ack[i] & commit_instr_id_commit[i].ex.valid & commit_instr_id_commit[i].ex.cause[63];
assign trace_o[i].cause = commit_instr_id_commit[i].ex.cause;
assign trace_o[i].tval = commit_instr_id_commit[i].ex.tval[31:0];
end
`endif
//pragma translate_off
`ifdef PITON_ARIANE
localparam PC_QUEUE_DEPTH = 16;
@ -990,51 +974,51 @@ module cva6 import ariane_pkg::*; #(
`endif // VERILATOR
//pragma translate_on
`ifdef RVFI_TRACE
always_comb begin
for (int i = 0; i < NR_COMMIT_PORTS; i++) begin
logic exception, mem_exception;
exception = commit_instr_id_commit[i].valid && ex_commit.valid;
mem_exception = exception &&
(ex_commit.cause == riscv::INSTR_ADDR_MISALIGNED ||
ex_commit.cause == riscv::INSTR_ACCESS_FAULT ||
ex_commit.cause == riscv::ILLEGAL_INSTR ||
ex_commit.cause == riscv::LD_ADDR_MISALIGNED ||
ex_commit.cause == riscv::LD_ACCESS_FAULT ||
ex_commit.cause == riscv::ST_ADDR_MISALIGNED ||
ex_commit.cause == riscv::ST_ACCESS_FAULT ||
ex_commit.cause == riscv::INSTR_PAGE_FAULT ||
ex_commit.cause == riscv::LOAD_PAGE_FAULT ||
ex_commit.cause == riscv::STORE_PAGE_FAULT);
// when rvfi_valid, the instruction is executed
rvfi_o[i].valid = (commit_ack[i] && !ex_commit.valid) ||
(exception && (ex_commit.cause == riscv::ENV_CALL_MMODE ||
ex_commit.cause == riscv::ENV_CALL_SMODE ||
ex_commit.cause == riscv::ENV_CALL_UMODE));
rvfi_o[i].insn = ex_commit.valid ? ex_commit.tval[31:0] : commit_instr_id_commit[i].ex.tval[31:0];
// when trap, the instruction is not executed
rvfi_o[i].trap = mem_exception;
rvfi_o[i].cause = ex_commit.cause;
rvfi_o[i].mode = debug_mode ? 2'b10 : priv_lvl;
rvfi_o[i].ixl = riscv::XLEN == 64 ? 2 : 1;
rvfi_o[i].rs1_addr = commit_instr_id_commit[i].rs1;
rvfi_o[i].rs2_addr = commit_instr_id_commit[i].rs2;
rvfi_o[i].rd_addr = commit_instr_id_commit[i].rd;
rvfi_o[i].rd_wdata = ariane_pkg::is_rd_fpr(commit_instr_id_commit[i].op) == 0 ? wdata_commit_id[i] : commit_instr_id_commit[i].result;
rvfi_o[i].pc_rdata = commit_instr_id_commit[i].pc;
`ifdef RVFI_MEM
rvfi_o[i].mem_addr = commit_instr_id_commit[i].lsu_addr;
// So far, only write paddr is reported. TODO: read paddr
rvfi_o[i].mem_paddr = mem_paddr;
rvfi_o[i].mem_wmask = commit_instr_id_commit[i].lsu_wmask;
rvfi_o[i].mem_wdata = commit_instr_id_commit[i].lsu_wdata;
rvfi_o[i].mem_rmask = commit_instr_id_commit[i].lsu_rmask;
rvfi_o[i].mem_rdata = commit_instr_id_commit[i].result;
rvfi_o[i].rs1_rdata = commit_instr_id_commit[i].rs1_rdata;
rvfi_o[i].rs2_rdata = commit_instr_id_commit[i].rs2_rdata;
`endif
if (ariane_pkg::RVFI) begin
always_comb begin
for (int i = 0; i < NR_COMMIT_PORTS; i++) begin
logic exception, mem_exception;
exception = commit_instr_id_commit[i].valid && ex_commit.valid;
mem_exception = exception &&
(ex_commit.cause == riscv::INSTR_ADDR_MISALIGNED ||
ex_commit.cause == riscv::INSTR_ACCESS_FAULT ||
ex_commit.cause == riscv::ILLEGAL_INSTR ||
ex_commit.cause == riscv::LD_ADDR_MISALIGNED ||
ex_commit.cause == riscv::LD_ACCESS_FAULT ||
ex_commit.cause == riscv::ST_ADDR_MISALIGNED ||
ex_commit.cause == riscv::ST_ACCESS_FAULT ||
ex_commit.cause == riscv::INSTR_PAGE_FAULT ||
ex_commit.cause == riscv::LOAD_PAGE_FAULT ||
ex_commit.cause == riscv::STORE_PAGE_FAULT);
// when rvfi_valid, the instruction is executed
rvfi_o[i].valid = (commit_ack[i] && !ex_commit.valid) ||
(exception && (ex_commit.cause == riscv::ENV_CALL_MMODE ||
ex_commit.cause == riscv::ENV_CALL_SMODE ||
ex_commit.cause == riscv::ENV_CALL_UMODE));
rvfi_o[i].insn = ex_commit.valid ? ex_commit.tval[31:0] : commit_instr_id_commit[i].ex.tval[31:0];
// when trap, the instruction is not executed
rvfi_o[i].trap = mem_exception;
rvfi_o[i].cause = ex_commit.cause;
rvfi_o[i].mode = debug_mode ? 2'b10 : priv_lvl;
rvfi_o[i].ixl = riscv::XLEN == 64 ? 2 : 1;
rvfi_o[i].rs1_addr = commit_instr_id_commit[i].rs1;
rvfi_o[i].rs2_addr = commit_instr_id_commit[i].rs2;
rvfi_o[i].rd_addr = commit_instr_id_commit[i].rd;
rvfi_o[i].rd_wdata = ariane_pkg::is_rd_fpr(commit_instr_id_commit[i].op) == 0 ? wdata_commit_id[i] : commit_instr_id_commit[i].result;
rvfi_o[i].pc_rdata = commit_instr_id_commit[i].pc;
rvfi_o[i].mem_addr = commit_instr_id_commit[i].lsu_addr;
// So far, only write paddr is reported. TODO: read paddr
rvfi_o[i].mem_paddr = mem_paddr;
rvfi_o[i].mem_wmask = commit_instr_id_commit[i].lsu_wmask;
rvfi_o[i].mem_wdata = commit_instr_id_commit[i].lsu_wdata;
rvfi_o[i].mem_rmask = commit_instr_id_commit[i].lsu_rmask;
rvfi_o[i].mem_rdata = commit_instr_id_commit[i].result;
rvfi_o[i].rs1_rdata = commit_instr_id_commit[i].rs1_rdata;
rvfi_o[i].rs2_rdata = commit_instr_id_commit[i].rs2_rdata;
end
end
end
`endif
endmodule // ariane

17
core/include/ariane_pkg.sv
View file

@ -662,6 +662,9 @@ package ariane_pkg;
// ---------------
// ID/EX/WB Stage
// ---------------
localparam RVFI = cva6_config_pkg::CVA6ConfigRvfiTrace;
typedef struct packed {
logic [riscv::VLEN-1:0] pc; // PC of instruction
logic [TRANS_ID_BITS-1:0] trans_id; // this can potentially be simplified, we could index the scoreboard entry
@ -683,14 +686,12 @@ package ariane_pkg;
branchpredict_sbe_t bp; // branch predict scoreboard data structure
logic is_compressed; // signals a compressed instructions, we need this information at the commit stage if
// we want jump accordingly e.g.: +4, +2
`ifdef RVFI_MEM
riscv::xlen_t rs1_rdata;
riscv::xlen_t rs2_rdata;
logic [riscv::VLEN-1:0] lsu_addr;
logic [(riscv::XLEN/8)-1:0] lsu_rmask;
logic [(riscv::XLEN/8)-1:0] lsu_wmask;
riscv::xlen_t lsu_wdata;
`endif
riscv::xlen_t rs1_rdata; // information needed by RVFI
riscv::xlen_t rs2_rdata; // information needed by RVFI
logic [riscv::VLEN-1:0] lsu_addr; // information needed by RVFI
logic [(riscv::XLEN/8)-1:0] lsu_rmask; // information needed by RVFI
logic [(riscv::XLEN/8)-1:0] lsu_wmask; // information needed by RVFI
riscv::xlen_t lsu_wdata; // information needed by RVFI
} scoreboard_entry_t;
// ---------------

9
core/include/cv32a60x_config_pkg.sv
View file

@ -70,4 +70,13 @@ package cva6_config_pkg;
localparam CVA6ConfigMmuPresent = 1;
`define RVFI_PORT
// Do not modify
`ifdef RVFI_PORT
localparam CVA6ConfigRvfiTrace = 1;
`else
localparam CVA6ConfigRvfiTrace = 0;
`endif
endpackage

10
core/include/cv32a6_embedded_config_pkg.sv
View file

@ -7,7 +7,6 @@
//
// Original Author: Jean-Roch COULON - Thales
package cva6_config_pkg;
typedef enum logic {
@ -70,4 +69,13 @@ package cva6_config_pkg;
localparam CVA6ConfigMmuPresent = 0;
`define RVFI_PORT
// Do not modify
`ifdef RVFI_PORT
localparam CVA6ConfigRvfiTrace = 1;
`else
localparam CVA6ConfigRvfiTrace = 0;
`endif
endpackage

9
core/include/cv32a6_ima_sv32_fpga_config_pkg.sv
View file

@ -70,4 +70,13 @@ package cva6_config_pkg;
localparam CVA6ConfigMmuPresent = 1;
`undef RVFI_PORT
// Do not modify
`ifdef RVFI_PORT
localparam CVA6ConfigRvfiTrace = 1;
`else
localparam CVA6ConfigRvfiTrace = 0;
`endif
endpackage

9
core/include/cv32a6_imac_sv0_config_pkg.sv
View file

@ -70,4 +70,13 @@ package cva6_config_pkg;
localparam CVA6ConfigMmuPresent = 1;
`define RVFI_PORT
// Do not modify
`ifdef RVFI_PORT
localparam CVA6ConfigRvfiTrace = 1;
`else
localparam CVA6ConfigRvfiTrace = 0;
`endif
endpackage

9
core/include/cv32a6_imac_sv32_config_pkg.sv
View file

@ -70,4 +70,13 @@ package cva6_config_pkg;
localparam CVA6ConfigMmuPresent = 1;
`define RVFI_PORT
// Do not modify
`ifdef RVFI_PORT
localparam CVA6ConfigRvfiTrace = 1;
`else
localparam CVA6ConfigRvfiTrace = 0;
`endif
endpackage

9
core/include/cv32a6_imafc_sv32_config_pkg.sv
View file

@ -70,4 +70,13 @@ package cva6_config_pkg;
localparam CVA6ConfigMmuPresent = 1;
`define RVFI_PORT
// Do not modify
`ifdef RVFI_PORT
localparam CVA6ConfigRvfiTrace = 1;
`else
localparam CVA6ConfigRvfiTrace = 0;
`endif
endpackage

9
core/include/cv64a6_imafdc_sv39_config_pkg.sv
View file

@ -70,4 +70,13 @@ package cva6_config_pkg;
localparam CVA6ConfigMmuPresent = 1;
`define RVFI_PORT
// Do not modify
`ifdef RVFI_PORT
localparam CVA6ConfigRvfiTrace = 1;
`else
localparam CVA6ConfigRvfiTrace = 0;
`endif
endpackage

9
core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv
View file

@ -70,4 +70,13 @@ package cva6_config_pkg;
localparam CVA6ConfigMmuPresent = 1;
`undef RVFI_PORT
// Do not modify
`ifdef RVFI_PORT
localparam CVA6ConfigRvfiTrace = 1;
`else
localparam CVA6ConfigRvfiTrace = 0;
`endif
endpackage

34
core/scoreboard.sv
View file

@ -96,14 +96,14 @@ module scoreboard #(
ariane_pkg::scoreboard_entry_t decoded_instr;
always_comb begin
decoded_instr = decoded_instr_i;
`ifdef RVFI_MEM
decoded_instr.rs1_rdata = rs1_forwarding_i;
decoded_instr.rs2_rdata = rs2_forwarding_i;
decoded_instr.lsu_addr = '0;
decoded_instr.lsu_rmask = '0;
decoded_instr.lsu_wmask = '0;
decoded_instr.lsu_wdata = '0;
`endif
if (ariane_pkg::RVFI) begin
decoded_instr.rs1_rdata = rs1_forwarding_i;
decoded_instr.rs2_rdata = rs2_forwarding_i;
decoded_instr.lsu_addr = '0;
decoded_instr.lsu_rmask = '0;
decoded_instr.lsu_wmask = '0;
decoded_instr.lsu_wdata = '0;
end
end
// output commit instruction directly
@ -155,16 +155,16 @@ module scoreboard #(
// ------------
// Write Back
// ------------
`ifdef RVFI_MEM
if (lsu_rmask_i != 0) begin
mem_n[lsu_addr_trans_id_i].sbe.lsu_addr = lsu_addr_i;
mem_n[lsu_addr_trans_id_i].sbe.lsu_rmask = lsu_rmask_i;
end else if (lsu_wmask_i != 0) begin
mem_n[lsu_addr_trans_id_i].sbe.lsu_addr = lsu_addr_i;
mem_n[lsu_addr_trans_id_i].sbe.lsu_wmask = lsu_wmask_i;
mem_n[lsu_addr_trans_id_i].sbe.lsu_wdata = wbdata_i[1];
if (ariane_pkg::RVFI) begin
if (lsu_rmask_i != 0) begin
mem_n[lsu_addr_trans_id_i].sbe.lsu_addr = lsu_addr_i;
mem_n[lsu_addr_trans_id_i].sbe.lsu_rmask = lsu_rmask_i;
end else if (lsu_wmask_i != 0) begin
mem_n[lsu_addr_trans_id_i].sbe.lsu_addr = lsu_addr_i;
mem_n[lsu_addr_trans_id_i].sbe.lsu_wmask = lsu_wmask_i;
mem_n[lsu_addr_trans_id_i].sbe.lsu_wdata = wbdata_i[1];
end
end
`endif
for (int unsigned i = 0; i < NR_WB_PORTS; i++) begin
// check if this instruction was issued (e.g.: it could happen after a flush that there is still

12
corev_apu/tb/ariane.sv
View file

@ -13,7 +13,7 @@
// Description: Ariane Top-level module
module ariane import ariane_pkg::*; #(
module ariane import ariane_pkg::*; import ariane_rvfi_pkg::*; #(
parameter ariane_pkg::ariane_cfg_t ArianeCfg = ariane_pkg::ArianeDefaultConfig,
parameter int unsigned AxiAddrWidth = ariane_axi::AddrWidth,
parameter int unsigned AxiDataWidth = ariane_axi::DataWidth,
@ -36,14 +36,10 @@ module ariane import ariane_pkg::*; #(
// Timer facilities
input logic time_irq_i, // timer interrupt in (async)
input logic debug_req_i, // debug request (async)
`ifdef FIRESIM_TRACE
// firesim trace port
output traced_instr_pkg::trace_port_t trace_o,
`endif
`ifdef RVFI_TRACE
`ifdef RVFI_PORT
// RISC-V formal interface port (`rvfi`):
// Can be left open when formal tracing is not needed.
output ariane_rvfi_pkg::rvfi_port_t rvfi_o,
output rvfi_port_t rvfi_o,
`endif
`ifdef PITON_ARIANE
// L15 (memory side)
@ -78,7 +74,7 @@ module ariane import ariane_pkg::*; #(
.ipi_i ( ipi_i ),
.time_irq_i ( time_irq_i ),
.debug_req_i ( debug_req_i ),
`ifdef RVFI_TRACE
`ifdef RVFI_PORT
.rvfi_o ( rvfi_o ),
`else
.rvfi_o ( ),

12
corev_apu/tb/ariane_testharness.sv
View file

@ -117,11 +117,11 @@ module ariane_testharness #(
assign debug_req_valid = (jtag_enable[0]) ? jtag_req_valid : dmi_req_valid;
assign debug_resp_ready = (jtag_enable[0]) ? jtag_resp_ready : dmi_resp_ready;
assign debug_req = (jtag_enable[0]) ? jtag_dmi_req : dmi_req;
`ifdef RVFI_TRACE
assign exit_o = (jtag_enable[0]) ? jtag_exit : rvfi_exit;
`else
assign exit_o = (jtag_enable[0]) ? jtag_exit : dmi_exit;
`endif
if (ariane_pkg::RVFI) begin
assign exit_o = (jtag_enable[0]) ? jtag_exit : rvfi_exit;
end else begin
assign exit_o = (jtag_enable[0]) ? jtag_exit : dmi_exit;
end
assign jtag_resp_valid = (jtag_enable[0]) ? debug_resp_valid : 1'b0;
assign dmi_resp_valid = (jtag_enable[0]) ? 1'b0 : debug_resp_valid;
@ -632,7 +632,7 @@ module ariane_testharness #(
.irq_i ( irqs ),
.ipi_i ( ipi ),
.time_irq_i ( timer_irq ),
`ifdef RVFI_TRACE
`ifdef RVFI_PORT
.rvfi_o ( rvfi ),
`endif
// Disable Debug when simulating with Spike

2
pd/synth/Makefile
View file

@ -30,7 +30,7 @@ endif
pre_cva6_synth:
grep "CVA6_REPO_DIR\}" ../../core/Flist.cva6|grep -v "instr_tracer"|grep -v "incdir" > Flist.cva6_synth
sed -i "s/^/analyze -f sverilog -define {RVFI_TRACE,RVFI_MEM} -lib ariane_lib /" Flist.cva6_synth
sed -i "s/^/analyze -f sverilog -lib ariane_lib /" Flist.cva6_synth
cva6_synth: pre_cva6_synth
@echo $(PERIOD)